3D Stacked Memory Architecture With Broadcast Inter-Die Data Transfer
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Solution Overview
Problem
The increasing data processing speed in memory devices leads to latency issues due to the separation of processors from memory, particularly in three-dimensional stacked semiconductor structures, where data transmission between processor and memory causes delays.
Innovation Solution
A memory device architecture that includes a buffer die and multiple core dies stacked on top of each other, utilizing through-silicon vias (TSVs) and common data input/output buses to facilitate efficient data movement between core dies, allowing for broadcast commands to manage data transfer without direct processor-memory interaction, thereby reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is transmitted between processor and memory in three-dimensional stacked structure, then data processing speed increases, but latency is caused due to separation of processor from memory
Solution Approach 1:
The memory device is segmented into multiple independent core dies (first core die, second core die, etc.), each capable of autonomous operation with its own processing circuit and memory cell array. This segmentation allows different core dies to operate independently, reducing the latency caused by data transmission between a centralized processor and memory by enabling local processing and storage operations.
2Productivity
If processor is separated from memory to enable three-dimensional stacking, then integration degree increases, but data transmission latency occurs
Solution Approach 1:
The patent transitions from a two-dimensional planar structure to a three-dimensional stacked structure by vertically stacking multiple core dies on the buffer die using through-silicon vias. This dimensional change enables higher integration density while incorporating broadcast command mechanisms that reduce latency by allowing simultaneous data distribution to multiple core dies without requiring sequential processor-memory transactions.
Solution Approach 2:
The buffer die acts as an intermediary between the external processor and the stacked core dies. It receives broadcast commands from the processor and distributes them to the appropriate core dies, mediating the data transmission process to reduce latency by enabling parallel data distribution rather than sequential access through the processor.
3Productivity
If multiple core dies are stacked to increase integration, then data processing capacity increases, but complexity of data management increases
Solution Approach 1:
The buffer die serves multiple functions: it acts as an interface to external devices, a command distribution center for broadcast commands, and a coordination hub for data transfer between core dies. This multi-functionality simplifies data management across multiple core dies by consolidating control functions in a single component rather than requiring complex inter-die communication protocols.
Solution Approach 2:
The buffer die mediates all data management operations between the external processor and the stacked core dies. It receives commands, decodes them, and distributes appropriate commands to specific core dies, thereby simplifying the complexity of managing multiple core dies by providing a centralized control interface that abstracts the underlying complexity from the external processor.
Data Source
AI summary
A memory device includes a buffer die configured to receive a first broadcast command and a second broadcast command from an external device; and a plurality of core dies stacked on the buffer die. The plurality of core dies include: a first core die including a first processing circuit, a first memory cell array, a first command decoder configured to decode the first broadcast command, and a first data input/output circuit configured to output data of the first memory cell array to a common data input/output bus under control of the first command decoder; and a second core die including a second processing circuit, a second memory cell array, a second command decoder configured to decode the second broadcast command, and a second data input/output circuit configured to receive the data of the first memory cell array through the common data input/output bus under control of the second command decoder.