3D Stacked Memory Core-Die Data Transfer With Broadcast Commands
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Solution Overview
Problem
The separation of a processor from a memory in semiconductor devices leads to latency in data transmission as data processing speeds increase, particularly in three-dimensional stacked memory structures using through silicon vias (TSVs).
Innovation Solution
A memory device with a buffer die and multiple core dies, each equipped with processing circuits and memory cell arrays, utilizes broadcast commands to facilitate direct data movement between core dies through common data and command buses, reducing latency by enabling simultaneous data processing and movement without the need for external read and write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is transmitted between processor and memory through external connections in three-dimensional stacked structure, then data processing speed increases, but transmission latency increases due to separation of processor and memory
Solution Approach 1:
The patent merges the processor and memory functions by integrating processing circuits within the memory device itself. Core dies include both memory cell arrays and processing circuits, allowing data to be processed directly where it is stored, eliminating the need for external data transmission and reducing latency while maintaining high processing speed.
Solution Approach 2:
The patent introduces an on-die buffer and command decoder as intermediaries between the external processor and memory cell arrays. These intermediaries handle data movement and command execution internally, reducing the need for external read/write operations and minimizing transmission latency while supporting high-speed data processing.
2Productivity
If multiple core dies are stacked to increase integration degree, then data processing capacity increases, but device complexity increases due to additional TSV connections and control circuits
Solution Approach 1:
The patent implements universal command decoders and data I/O circuits that can handle multiple operations (read, write, data movement between cores) through a single set of external connections. The buffer die serves multiple functions including receiving commands from external devices, routing them to appropriate core dies, and managing data transfer between cores, thereby reducing the need for separate dedicated circuits for each function.
Solution Approach 2:
The patent segments the memory device into multiple independent core dies, each with its own processing circuit and memory cell array. This segmentation allows each core to operate independently on its own data, increasing overall processing capacity while the shared buffer and command interface manage the complexity of inter-core communication through standardized protocols.
3Loss of time
If broadcast commands are used for data movement between core dies, then external read and write operations are eliminated reducing latency, but command decoding complexity increases
Solution Approach 1:
The command decoder is designed as a universal decoder that can interpret multiple types of commands (read, write, data movement between cores) through a single standardized interface. The buffer die receives all commands externally and routes them to appropriate core dies, while each core's decoder handles multiple operation types, reducing the need for separate dedicated decoding circuits for each operation type.
Data Source
AI summary
A memory device includes a buffer die configured to receive a first broadcast command and a second broadcast command from an external device; and a plurality of core dies stacked on the buffer die. The plurality of core dies include: a first core die including a first processing circuit, a first memory cell array, a first command decoder configured to decode the first broadcast command, and a first data input/output circuit configured to output data of the first memory cell array to a common data input/output bus under control of the first command decoder; and a second core die including a second processing circuit, a second memory cell array, a second command decoder configured to decode the second broadcast command, and a second data input/output circuit configured to receive the data of the first memory cell array through the common data input/output bus under control of the second command decoder.