Stacked Memory Semiconductor Package With Buffer Chip Routing
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Solution Overview
Problem
The challenge is to create a semiconductor package that can accommodate multiple memory chips while maintaining a compact size, as electronic products require high performance and data processing capabilities in increasingly smaller form factors, and existing solutions struggle to efficiently integrate buffer chips and memory chips within a minimal footprint.
Innovation Solution
The semiconductor package design includes a substrate with a buffer chip and multiple memory chips connected via redistribution lines and bonding wires, where the buffer chip is connected to both memory chips and the substrate, allowing for efficient data transmission and a reduced package size through strategic placement of internal and external channel pads and a molding layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple memory chips are integrated with a buffer chip in a single package, then data processing performance and operating speed are improved, but the package size and thickness increase
Solution Approach 1:
The patent transitions from a planar arrangement to a three-dimensional stacked configuration where memory chips are positioned at different vertical levels relative to the buffer chip. The first memory chip is disposed at a first level and the second memory chip at a second level, utilizing the vertical dimension to accommodate multiple chips without increasing the package footprint.
Solution Approach 2:
The patent implements a nested structure where memory chips are positioned within the vertical space above the buffer chip. The first and second memory chips are nested at different heights, with each chip occupying a distinct vertical level, allowing multiple chips to be integrated within a compact footprint similar to a single chip layout.
2Length of stationary object
If memory chips are positioned closer to the buffer chip, then package thickness is reduced, but wiring complexity and signal transmission challenges increase
Solution Approach 1:
The patent segments the package into distinct vertical levels, with the buffer chip at a base level and memory chips at elevated levels. This segmentation allows for organized signal routing where bonding wires connect specific pads on the buffer chip to corresponding pads on memory chips at different levels, managing complexity through structured spatial organization.
Solution Approach 2:
The patent uses bonding wires as intermediary connectors between the buffer chip and memory chips. These bonding wires serve as flexible conduits that can span the vertical distance between chips while maintaining electrical connections, effectively mediating the signal transmission between components at different levels without requiring rigid printed circuit board traces.
3Area of stationary object
If channel pads are strategically positioned on the buffer chip, then package footprint is minimized, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs asymmetric positioning of channel pads on the buffer chip, with first channel pads located at a first position and second channel pads at a second position that is offset from the first position. This asymmetric arrangement optimizes space utilization and allows for compact packaging while the precise positioning is achieved through controlled manufacturing processes.
Data Source
AI summary
A semiconductor package may include: a substrate; a first sub-semiconductor package disposed over the substrate, the first sub-semiconductor package including a first buffer chip and a first memory chip; and a second memory chip disposed over the first sub-semiconductor package, wherein the first buffer chip and the first memory chip are connected to each other using a first redistribution line, and wherein the first buffer chip and the second memory chip are connected to each other using a second bonding wire.