Stacked Memory and Cache Circuit Layout for High-I/O Integration
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing processing units and memory circuits with different electrical characteristics on the same die, as it is not economically feasible, and existing packaging technologies like 2.5D and 3D IC packaging struggle to accommodate varying I/O terminals effectively.
Innovation Solution
The implementation of a memory circuit configuration that includes a primary memory circuit and a cache memory circuit, each with distinct memory cells types, coupled via separate controller circuits, allowing for efficient data access and management through a hybrid 2.5D/3D IC packaging approach, enabling faster read/write operations and configurable access channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If processing unit and memory circuit are manufactured on the same die using the same manufacturing process, then device complexity is reduced, but manufacturing precision and electrical characteristics cannot be optimized for each component type
Solution Approach 1:
The system is divided into separate processing unit die and memory circuit die, each optimized for their specific functions and manufactured using appropriate processes, then integrated through 2.5D/3D packaging with interposers and through-silicon vias
Solution Approach 2:
The patent transitions from traditional 2D planar integration to 2.5D and 3D vertical integration, stacking memory dies over processing dies and using interposers to enable high-density I/O connections without increasing footprint area
2Ease of manufacture
If conventional 2D IC packaging is used, then manufacturing is simpler, but I/O terminal capacity is limited
Solution Approach 1:
The patent employs 2.5D IC packaging where multiple memory dies are arranged in a grid pattern on an interposer substrate, and 3D IC packaging where memory dies are stacked vertically over processing dies, dramatically increasing I/O terminal capacity while maintaining compact form factor
Solution Approach 2:
Interposer substrates with through-silicon vias and redistribution layers serve as intermediary components, enabling high-density interconnections between processing units and memory circuits while providing mechanical support and signal routing
3Quantity of substance
If 2.5D IC packaging is used to increase I/O terminals, then connectivity capacity improves, but manufacturing complexity increases
Solution Approach 1:
The interposer substrate performs multiple functions simultaneously: mechanical support for stacked dies, electrical interconnection through through-silicon vias, signal redistribution through copper traces, and thermal management, thereby managing complexity through functional integration
4Reliability
If separate dies are used for processing and memory units, then electrical characteristics are optimized, but integration density decreases
Solution Approach 1:
The patent utilizes vertical stacking in 3D IC packaging to place memory dies directly over processing dies, utilizing the third dimension (height) to achieve high integration density while maintaining separate optimization of electrical characteristics for each component type
Data Source
AI summary
A memory system includes multiple groups of primary memory cells residing in a first die or a stack of first dies, multiple groups of cache memory cells residing in a second die, an interposer, and control circuits residing in a third die. Each group of the cache memory cells is associated with a corresponding group of the primary memory cells. The first die or the stack of first dies is coupled to a top surface of the second die through a first group of bumps. A bottom surface of the second die is coupled to a top surface of the interposer through a second group of bumps. The control circuits are associated with the primary memory cells and the cache memory cells. The third die is positioned aside the second die and coupled to the top surface of the interposer through a third group of pumps.