Stacked Memory Cache Repair for Failed Access Addresses
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Solution Overview
Problem
Stacked memory systems face challenges in efficiently handling data failures during memory access operations due to the complexity of high-speed data transmission and communication, particularly in high bandwidth memory (HBM) systems, where failures can disrupt data integrity and require effective repair mechanisms.
Innovation Solution
The memory device incorporates a cache memory and a repair control circuit to store access addresses and data during failures, enabling cache and core operations based on address matching, and periodically checks access addresses to determine necessary repair operations, including soft-post package repairs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a cache memory is introduced to store access addresses and data during failures, then data integrity is improved, but device complexity increases
Solution Approach 1:
A cache memory is introduced as an intermediary component between the memory chip and the base chip to store access addresses and data during failures. This mediator allows the system to buffer failed data temporarily and perform repairs without disrupting the overall memory operation, thereby improving data integrity while managing complexity through a dedicated intermediate storage layer.
Solution Approach 2:
The memory system is segmented into functional components: a memory chip for data storage, a base chip for control, and a cache memory for failure handling. This segmentation allows each component to specialize in specific tasks, with the cache memory dedicated to handling failures, thus improving reliability without significantly increasing overall device complexity.
2Reliability
If periodic checking of access addresses is performed to determine repair operations, then reliability is improved, but loss of time increases
Solution Approach 1:
The repair control circuit performs periodic checking of access addresses stored in the cache memory at predetermined intervals. This periodic action allows the system to monitor for failures and initiate repair operations at appropriate times without continuously monitoring every access, thereby improving reliability while minimizing time loss through scheduled rather than continuous checking.
Solution Approach 2:
Access addresses are pre-stored in the cache memory when failures occur, and the repair control circuit checks these stored addresses periodically to determine if repair operations are needed. This preliminary storage of address information allows for faster repair decision-making compared to analyzing failure data in real-time, reducing the time loss associated with repair operations.
3Productivity
If high-speed data transmission is implemented in stacked memory systems, then productivity is improved, but object-generated harmful factors increase
Solution Approach 1:
The system converts the harmful effect of data failures into a beneficial repair mechanism. When data failures occur during high-speed transmission, the repair control circuit detects these failures and automatically performs repair operations using stored access addresses from the cache memory. This transforms the harmful data failures into an opportunity for proactive repair, maintaining high bandwidth while mitigating the impact of transmission errors.
Data Source
AI summary
A memory device includes a memory chip disposed over a base chip. The base chip includes a cache memory configured to store a first access address and first access data when a failure occurs in the first access data during a first memory access operation, and a repair control circuit configured to perform a cache write operation and a cache read operation on the cache memory when a second access address received in a second memory access operation is the same as addresses stored in the cache memory and configured to perform a core write operation and a core read operation on the memory chip when the second access address is different from the addresses stored in the cache memory.