Stacked Memory Chip Layout for Higher Capacitance Density
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Solution Overview
Problem
Conventional memory devices have chip sizes that are proportionally determined by the size of the peripheral circuit, limiting the integration and capacitance of the memory cell arrays.
Innovation Solution
The memory device is configured with multiple chips, including peripheral circuit chips and cell chips stacked in a manner that allows for increased peripheral circuit area without proportionally increasing the chip size, by placing peripheral circuit regions at both ends of the chip stack and forming memory cell arrays in multiple cell chips, thereby doubling the peripheral circuit area and increasing memory capacitance per unit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the peripheral circuit size is increased to improve functionality, then the chip size proportionally increases, but the memory capacitance per unit area decreases
Solution Approach 1:
The memory device is divided into multiple chips (first chip, second chip, third chip) with distinct functions. The first and third chips contain peripheral circuits, while the second chip contains memory cell arrays. This segmentation allows the peripheral circuit area to be increased without proportionally increasing the overall chip size, as multiple chips are stacked together to form the complete device.
Solution Approach 2:
The patent transitions from a two-dimensional planar layout to a three-dimensional stacked configuration. By stacking multiple chips vertically, the peripheral circuit area is effectively doubled (with peripheral circuits on both first and third chips) without proportionally increasing the footprint area, thereby increasing memory capacitance per unit area.
2Quantity of substance
If multiple chips are stacked to increase peripheral circuit area, then memory capacitance per unit area increases, but device complexity increases
Solution Approach 1:
Multiple chips are merged into a single stacked structure to achieve higher memory capacitance. The first chip with peripheral circuit, second chip with memory cell arrays, and third chip with peripheral circuit are bonded together, combining their functions into one integrated device that achieves doubled peripheral circuit area and increased memory capacitance.
3Adaptability or versatility
If peripheral circuits are formed on both ends of chip stack, then peripheral circuit area is doubled, but manufacturing process complexity increases
Solution Approach 1:
The peripheral circuits on the first and third chips are formed in advance before stacking. This preliminary formation of peripheral circuits on both end chips allows for parallel processing during manufacturing, where the first, second, and third chips can be prepared simultaneously and then bonded together, reducing overall manufacturing time and complexity.
Data Source
AI summary
According to one embodiment, a memory device includes a first chip and a second chip provided over the first chip. The first chip includes a first substrate, a first electrode, and a first memory cell array provided between the first substrate and the first electrode. The second chip includes a second substrate, a second electrode in contact with the first electrode, and a second memory cell array provided between the second substrate and the second electrode.