Stacked Memory Capacitor Placement for Chip Area Reduction
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Solution Overview
Problem
The challenge in stacked type NAND type flash memory devices is to efficiently dispose control circuits underneath the memory cell array to minimize chip area while avoiding increased parasitic capacitance and maintaining efficient operation.
Innovation Solution
A nonvolatile semiconductor memory device configuration with a power supply circuit that includes a boost circuit and a switch, where a capacitor of larger capacitance is placed directly below the memory cell array to manage voltage and charging, and a boost circuit charges the capacitor using a constant current based on control signals to optimize voltage adjustment and reduce chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If control circuits are disposed underneath the memory cell array to minimize chip area, then chip area is reduced, but parasitic capacitance increases
Solution Approach 1:
The patent transitions from planar arrangement to three-dimensional stacked architecture, where memory cells are arranged vertically in multiple layers above the substrate. Control circuits remain on the substrate plane while memory cells extend in the vertical dimension, achieving area reduction without forcing control circuits underneath memory cells.
Solution Approach 2:
The memory cell array is segmented into multiple stacked layers (first memory cell layer, second memory cell layer, etc.), each independently controllable. This segmentation allows selective activation of specific layers, reducing the active capacitance load on control circuits at any given time.
2Productivity
If a larger capacitor is placed directly below the memory cell array, then voltage management efficiency is improved, but circuit area increases
Solution Approach 1:
The capacitor serves multiple functions: voltage management for the memory cell array, power supply stabilization, and potential energy storage for rapid operations. This multi-functionality justifies its prominent placement and larger size without requiring additional dedicated components.
Solution Approach 2:
The power supply circuit is merged with the capacitor into a integrated power management unit. The booster circuit, capacitor, and control logic are combined into a single functional block, optimizing space utilization while maintaining efficient voltage management.
3Quantity of substance
If memory cells are stacked vertically to improve integration density, then degree of integration is improved, but control circuit complexity increases
Solution Approach 1:
The vertically stacked memory cells are divided into multiple independently addressable layers. Each layer can be selectively activated and controlled, allowing the control circuit to manage only the active layer at any given time rather than managing all layers simultaneously, thus reducing control complexity.
Solution Approach 2:
Word lines serve as intermediary elements between the control circuit and the stacked memory cells. The control circuit activates specific word lines to select particular layers, providing a simplified interface for managing the complex three-dimensional memory structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the chip area by allowing a larger capacitor to be placed underneath the memory cell array without increasing the circuit area, improving operational efficiency and enabling more efficient data transfer in systems like Solid State Drives by reducing peak current requirements.
Implementation Method 1
a capacitor (CAP) having one end connected to the output terminal, and the other end connected to the boost circuit, and configured to adjust a voltage of an output terminal
Implementation Method 2
a boost circuit connected to the other end of the capacitor, and configured to charge the capacitor using a constant current of a certain current value
Data Source
AI summary
A nonvolatile semiconductor memory device according to an embodiment includes: a semiconductor substrate; a memory cell array including a plurality of memory cells, the memory cells being stacked on the semiconductor substrate; and a power supply circuit provided on the semiconductor substrate. The power supply circuit includes: a pump circuit configured to generate a voltage and supply the voltage to the memory cell array; a limiter circuit configured to output control signal for activating the pump circuit according to a comparison result between a voltage value of the output terminal and a first value; a capacitor configured to adjust a voltage of the output terminal; a boost circuit configured to charge the capacitor using a constant current based on the control signal; and a switch configured to stop a charge operation of the boost circuit. The capacitor is provided directly below the memory cell array.