3D Stacked Memory Cell Arrays for Capacity and Yield
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Solution Overview
Problem
Existing memory devices face challenges in achieving high data storage capacity and yield, particularly in two-dimensional configurations.
Innovation Solution
A three-dimensional memory device is designed with stacked structures, including a first structure with peripheral circuitry and auxiliary memory cell arrays, and a second structure with main memory cell arrays, connected via bonding pads and interconnect structures, allowing for increased storage capacity and improved yield through the use of auxiliary memory cells to supplement or repair main memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional memory cell arrangement is used, then device structure is simple, but data storage capacity is limited
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional stacked structure, where multiple memory cell arrays are stacked vertically on separate substrates. This dimensional change enables significantly increased storage capacity by utilizing vertical space rather than only horizontal plane, directly resolving the contradiction between storage capacity and structural simplicity.
2Quantity of substance
If auxiliary memory cell arrays are added to increase storage capacity, then data storage capacity increases, but device complexity increases
Solution Approach 1:
The auxiliary memory cell arrays are designed to serve multiple functions: they provide additional storage capacity and can also function as repair resources for defective main memory cells. This multi-functionality allows the system to achieve increased storage capacity while managing complexity through versatile component design, where the same auxiliary arrays serve both expansion and reliability purposes.
Solution Approach 2:
The patent combines the auxiliary memory cell arrays with the main memory cell arrays into a unified memory system that shares common peripheral circuitry and control mechanisms. By merging these arrays under a single operational framework with shared resources, the system achieves increased storage capacity while avoiding proportional increases in overall system complexity.
3Quantity of substance
If multiple substrates are stacked to increase storage capacity, then storage capacity increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the memory system into multiple independent substrates (first substrate with main memory cell array, second substrate with auxiliary memory cell array) that can be manufactured and tested separately before final assembly. This segmentation allows each substrate to be optimized and validated independently, reducing the overall manufacturing precision requirements compared to attempting to create a monolithic multi-layer structure in a single fabrication process.
Data Source
AI summary
A memory device is provided. The memory device includes a first structure and a second structure stacked on the first structure in a vertical direction. The first structure includes a first substrate, peripheral circuitry, an auxiliary memory cell array, a first insulating layer, and a plurality of first bonding pads. The second structure includes a second substrate, a main memory cell array, a second insulating layer, and a plurality of second bonding pads. The plurality of first bonding pads are in contact with the plurality of second bonding pads, respectively.