Vertically Stacked Memory Cell Parasitic Capacitance Reduction
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Solution Overview
Problem
The shrinking of memory cells in semiconductor devices faces structural limitations that hinder the reduction of parasitic capacitance and increase in memory cell density, making it difficult to enhance memory capacity effectively.
Innovation Solution
The implementation of vertically stacked active layers with horizontally extending bit lines and vertically oriented word lines, along with interconnections that form a chain structure to reduce the number of access lines, allowing for increased memory cell density and reduced parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is reduced to increase density, then memory capacity increases, but parasitic capacitance reduction becomes difficult due to structural limitations
Solution Approach 1:
The patent transitions from planar memory cell layout to three-dimensional vertically stacked structure. Multiple active layers are stacked along the vertical direction (first direction) over the substrate, with word lines extending vertically through multiple active layers. This dimensional change allows increased memory cell density without proportionally increasing parasitic capacitance, as the vertical stacking efficiently utilizes the third dimension while maintaining compact interconnection paths.
2Quantity of substance
If vertically stacked active layers are implemented to increase density, then memory cell density improves, but interconnection complexity increases
Solution Approach 1:
The interconnection structure is segmented into distinct functional components: bit lines coupled to first sides of active layers, word lines vertically extending through active layers, plate lines coupled to second sides of active layers, and capacitors coupled to the second sides. This segmentation allows each interconnection element to be optimized independently while managing the overall complexity of the three-dimensional structure.
Solution Approach 2:
The word lines serve multiple functions by vertically extending through multiple active layers, enabling a single word line to control multiple memory cell stacks simultaneously. Similarly, bit lines and plate lines are configured to interface with multiple active layers, reducing the total number of interconnection lines needed while maintaining access to all memory cells in the stacked structure.
3Device complexity
If word lines are vertically oriented through active layers to reduce access line count, then the number of access lines decreases, but manufacturing precision requirements increase
Solution Approach 1:
The methodology establishes preliminary structural frameworks before forming the vertical word lines. Active layers are first formed in stacked configuration with defined spatial relationships, and bit lines and plate lines are pre-positioned at respective sides of the active layers. This preliminary arrangement provides alignment references that guide subsequent vertical word line formation, ensuring precise registration through the stacked structure without requiring de novo alignment procedures.
Data Source
AI summary
The present disclosure technology provides memory cells and a semiconductor device including the same. According to the present technology, a semiconductor device comprises a plurality of active layers vertically stacked along a first direction over a substrate and horizontally extending along a second direction crossing the first direction; a plurality of bit lines coupled to respective first sides of the active layers and horizontally extending in a third direction crossing the first direction and the second direction; a plurality of capacitors coupled to respective second sides of the active layers; a word line vertically extending through the active layers along the first direction; an upper-level interconnection coupled to an upper end of the word line; and a lower-level interconnection coupled to a lower end of the word line.