3D Stacked Memory Cell Mat with Mid-Point Contacts

The patent transitions from a two-dimensional planar cell mat structure to a three-dimensional stacked structure with multiple planes (first plane, second plane, third plane) vertically arranged. This dimensional change allows memory cells to be organized in multiple layers, increasing the number of accessible memory cells while maintaining shorter current paths within each plane, thereby reducing line resistance and voltage drop effects.

The cell mat is divided into multiple separate planes stacked vertically, with each plane containing a subset of memory cells. This segmentation allows each plane to have its own dedicated lower lines and upper lines, distributing the current load and reducing the overall line resistance. The segmented structure also enables better voltage distribution across the memory array.

By stacking multiple planes vertically, the patent reduces the horizontal footprint of the memory unit while maintaining adequate line lengths for reliable operation. The vertical stacking allows the memory array to fit in a smaller planar area without proportionally increasing line resistance, as each plane can be optimized independently for its line dimensions.

Each plane in the stacked structure can have locally optimized line dimensions and contact configurations tailored to its specific requirements. This allows different planes to have different line widths, lengths, or contact positions, enabling each local region to achieve optimal resistance characteristics while contributing to the overall compact structure.