Stacked Memory Cell Reading With Current Comparison for Shorter Access Time
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory devices face challenges with increased access time and power consumption due to large numbers of memory cells connected to a bit line, particularly when using current sensing amplifiers, and require a reduced circuit area for efficient data reading.
Innovation Solution
A memory device structure with stacked layers, including a reading circuit and memory cells connected through wirings, utilizes transistors with silicon and metal oxide in the channel formation region, employing current comparison for data reading to reduce access time and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a current sensing amplifier is used for data reading, then access time is shortened, but power consumption increases
Solution Approach 1:
The patent divides the sensing function into two separate circuits: a voltage sensing amplifier for reading data and a current sensing amplifier for sensing current. This segmentation allows each circuit to be optimized for its specific function, enabling fast access through voltage sensing while using current sensing only when necessary, thus reducing overall power consumption compared to always using a current sensing amplifier.
Solution Approach 2:
The patent dynamically switches between voltage sensing and current sensing modes based on the state of the bit line. The voltage sensing amplifier is used during normal read operations for fast access, while the current sensing amplifier is activated only when the bit line voltage is insufficient, providing adaptive performance optimization and power management.
2Quantity of substance
If more memory cells are electrically connected to one bit line to increase storage capacity, then storage capacity per unit area increases, but access time increases
Solution Approach 1:
The patent transitions from a planar memory architecture to a three-dimensional stacked architecture with multiple memory cell layers connected to bit lines. This dimensional change allows increasing the number of memory cells per bit line without proportionally increasing access time, as the stacked structure enables parallel access to multiple layers simultaneously, thus improving storage capacity while maintaining acceptable access times.
3Use of energy by moving object
If a voltage sensing amplifier is used for data reading, then power consumption is reduced, but access time increases due to long precharge and discharge times
Solution Approach 1:
The patent divides the sensing function into two separate circuits: a voltage sensing amplifier for reading data and a current sensing amplifier for sensing current. This segmentation allows each circuit to be optimized for its specific function, enabling fast access through voltage sensing while using current sensing only when necessary, thus reducing overall power consumption compared to always using a current sensing amplifier.
Solution Approach 2:
The patent dynamically switches between voltage sensing and current sensing modes based on the state of the bit line. The voltage sensing amplifier is used during normal read operations for fast access, while the current sensing amplifier is activated only when the bit line voltage is insufficient, providing adaptive performance optimization and power management.
Data Source
AI summary
A memory device with shortened access time in data reading is provided. The memory device includes a first layer and a second layer positioned above the first layer, the first layer includes a reading circuit, and the second layer includes a first memory cell and a second memory cell. The reading circuit includes a Si transistor. The first memory cell and the second memory cell each include an OS transistor. The first memory cell is electrically connected to the reading circuit, and the second memory cell is electrically connected to the reading circuit. When a first current corresponding to first data retained in the first memory cell flows from the reading circuit to the first memory cell and a second current corresponding to second data retained in the second memory cell flows from the reading circuit to the second memory cell, the reading circuit compares the current amounts of the first current and the second current, and reads the first data.