Stacked Oxide-Semiconductor Memory Cell for High-Density Retention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory devices face challenges in occupying a small area, achieving high storage capacity, ensuring high reliability, and being manufactured at low cost.
Innovation Solution
A memory cell design incorporating a reading transistor and a writing transistor, with the writing transistor positioned above the reading transistor, utilizing oxide semiconductors for the semiconductor layers, and arranging memory cells in a matrix configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If memory cells are arranged in a conventional planar configuration, then the device occupies a large area, but the storage capacity per unit area is reduced
Solution Approach 1:
The patent implements a three-dimensional stacked memory architecture where memory cells are arranged in multiple layers vertically. Each memory cell includes a transistor and capacitor stacked in the vertical direction, with interlayer insulating films separating the layers. This vertical stacking enables high-density storage by utilizing the third dimension (height) rather than only expanding in the planar direction, thereby increasing storage capacity per unit area while occupying a smaller footprint on the substrate.
2Reliability
If conventional semiconductor materials are used, then manufacturing is simpler, but off-state current is high and data retention is poor
Solution Approach 1:
The patent changes the material parameter from conventional silicon-based semiconductors to oxide semiconductors (such as IGZO - indium gallium zinc oxide). This material substitution fundamentally alters the electrical characteristics, achieving extremely low off-state current (on the order of 10^-21 to 10^-24 A) and enabling nonvolatile memory operation with long data retention. The oxide semiconductor layer is formed using sputtering or atomic layer deposition (ALD) techniques, which, while adding manufacturing steps, provide precise control over film thickness and composition to achieve the desired electrical properties.
3Reliability
If oxide semiconductors are used for both reading and writing transistors, then data retention is improved, but the writing transistor may not provide sufficient drive current
Solution Approach 1:
The patent applies different semiconductor materials to different transistor types within the same memory cell based on their specific functional requirements. The writing transistor, which requires high drive current for data writing operations, uses a high-mobility semiconductor material (such as silicon-based semiconductor). The reading transistor and transistor for data retention, which require low off-state current, use oxide semiconductor materials. This localized material assignment optimizes the performance of each transistor for its specific function while maintaining overall cell efficiency.
4Reliability
If more transistors and capacitors are added to each memory cell, then functionality is improved, but the cell area increases
Solution Approach 1:
The patent implements a three-dimensional stacked memory architecture where memory cells are arranged in multiple layers vertically. Each memory cell includes a transistor and capacitor stacked in the vertical direction, with interlayer insulating films separating the layers. This vertical stacking enables high-density storage by utilizing the third dimension (height) rather than only expanding in the planar direction, thereby increasing storage capacity per unit area while occupying a smaller footprint on the substrate.
Solution Approach 2:
The patent designs the memory cell structure to share common components and wiring across multiple functional units. For example, bit lines and word lines are shared among multiple memory cells in the same column or row. The stacked transistor-capacitor structure serves multiple functions: the transistor provides both writing and reading capability, while the capacitor stores data. This multi-functionality reduces the number of discrete components needed per cell, thereby reducing overall cell area while maintaining full functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves a memory device that occupies a small area, has high storage capacity, is highly reliable, and is manufactured at low cost, with oxide semiconductors providing low off-state current and long data retention.
Implementation Method 1
OS transistors have an extremely low off-state current. By utilizing this fact, OS transistors are used in nonvolatile memories
Implementation Method 2
a memory cell which includes a reading transistor, a writing transistor, and a capacitor
Data Source
AI summary
A memory device occupying a small area is provided. In a memory cell including a reading transistor, a writing transistor, and a capacitor, the writing transistor is provided above the reading transistor. Alternatively, the reading transistor is provided above the writing transistor. An oxide semiconductor is used for a semiconductor layer where a channel of the writing transistor is formed. An oxide semiconductor is used for a semiconductor layer where a channel of the reading transistor is formed. Memory cells are arranged in a matrix.