Dual-Layer Nonvolatile Memory Structure for Compact Wider Cell Spacing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing nonvolatile memory devices face challenges in increasing the separation spacing between adjacent memory elements while maintaining a compact memory cell size, which affects fabrication processes and memory performance.
Innovation Solution
The implementation of a nonvolatile memory device with dual memory layers, where the first and second memory elements are formed at different levels and connected to respective drains, allowing for an increased center-to-center distance between memory elements by a factor of √2, thereby easing processing constraints and enhancing memory performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the minimum feature size is shrunk to increase device density, then the device density increases, but the center-to-center spacing between adjacent memory elements decreases, affecting fabrication processes and memory performance
Solution Approach 1:
The patent transitions from a single-layer memory element arrangement to a dual-layer three-dimensional configuration. Memory elements are stacked at different vertical levels (first and second levels) with interconnect structures connecting corresponding drains between layers. This vertical stacking approach increases device density while maintaining adequate horizontal spacing between adjacent memory elements, thereby resolving the contradiction between high density and sufficient spacing for fabrication and performance.
2Ease of manufacture
If the center-to-center distance between memory elements is increased to ease processing constraints, then fabrication becomes easier, but the memory cell size increases
Solution Approach 1:
By stacking memory elements vertically at two different levels and using interconnect structures to connect corresponding drains between layers, the patent achieves adequate center-to-center spacing for ease of manufacturing (ion milling, etc.) without increasing the planar footprint of each memory cell. The vertical dimension provides the additional space needed for processing while maintaining compact cell area.
3Area of stationary object
If a compact cell structure is used to reduce memory cell size, then the memory cell area decreases, but the center-to-center spacing between adjacent memory elements becomes insufficient
Solution Approach 1:
The patent employs a three-dimensional dual-layer structure where memory elements are positioned at different vertical levels. This allows the horizontal center-to-center spacing between adjacent memory elements to be increased for adequate separation, while the vertical stacking maintains a compact overall cell area. The interconnect structures efficiently route connections between layers without consuming excessive planar space.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases the minimum center-to-center distance between adjacent memory elements, easing processing constraints and potentially improving memory performance by allowing for different types of memory elements with varying characteristics to be incorporated.
Implementation Method 1
When the magnetization directions of the magnetic free and reference layers are substantially parallel or oriented in a same direction, electrons polarized by the magnetic reference layer can tunnel through the insulating tunnel junction layer, thereby decreasing the electrical resistance of the MTJ. Conversely, the electrical resistance of the MTJ is high when the magnetization directions of the magnetic free and reference layers are substantially anti-parallel or oriented in opposite directions.
Implementation Method 2
electrons polarized by the magnetic reference layer can tunnel through the insulating tunnel junction layer
Data Source
AI summary
The present invention is directed to a nonvolatile memory device including a plurality of first conductive lines extending along a first direction; first and second plurality of second conductive lines extending along a second direction; an array of active regions, each active region having an elongated shape directed along a third direction substantially bisecting an angle formed between the first and second directions and including first and second drains formed at opposite ends thereof; and an array of first memory elements and an array of second memory elements formed at different levels, each first memory element and each second memory element being electrically connected to a respective first drain and a respective second drain, respectively. The first and second plurality of second conductive lines are electrically connected to the array of first memory elements and the array of second memory elements along the second direction, respectively.