3D Memory Structure With Staggered Cell Stacks for Easier Routing
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Solution Overview
Problem
The semiconductor industry faces challenges in simplifying the fabrication process and reducing costs as feature sizes decrease, particularly in the alignment and connection of source and drain regions in 3D memory structures, which complicates the formation of circuit components and increases complexity.
Innovation Solution
The proposed solution involves a 3D memory structure with vertically stacked memory cells, where the arrangement of memory cells and the routing/connections of the source line and bit line arrays are adjusted to simplify the process flow, using a staggered layout and shared word lines and source/bit lines to reduce the number of photomasks and fabrication steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional alignment and connection methods are used for source and drain regions in 3D memory structures, then manufacturing precision can be maintained, but device complexity and fabrication process complexity increase significantly
Solution Approach 1:
The patent transitions from planar 2D alignment to 3D staggered alignment, where source and drain regions are positioned at different vertical levels. This dimensional change allows regions that would otherwise require precise lateral alignment to instead be connected through vertical vias, significantly reducing alignment complexity while maintaining manufacturing precision.
Solution Approach 2:
The patent divides the connection path into multiple segments: lower source/drain regions connected to intermediate conductors, and upper source/drain regions connected to other intermediate conductors, with each segment handled by separate photomasks. This segmentation allows independent optimization of each alignment step rather than requiring all regions to align in a single complex step.
2Ease of manufacture
If the number of photomasks and fabrication steps is reduced to simplify the process, then ease of manufacture improves, but manufacturing precision may deteriorate
Solution Approach 1:
The fabrication process is segmented into distinct stages, each handled by a separate photomask. The first photomask forms lower source/drain regions and intermediate conductors, while the second photomask forms upper source/drain regions. This segmentation simplifies each individual step while maintaining overall precision through cumulative alignment.
Solution Approach 2:
The patent performs preliminary formation of lower source/drain regions and intermediate conductors before forming upper source/drain regions. This preliminary action establishes a foundation that guides subsequent alignment, making the overall process easier to manufacture while maintaining precision through staged construction.
3Productivity
If feature sizes are reduced to increase integration density, then productivity improves, but device complexity and fabrication difficulty increase
Solution Approach 1:
By utilizing vertical stacking with staggered source and drain regions at different heights, the patent increases integration density without proportionally increasing lateral feature complexity. The 3D arrangement allows more memory cells to be packed in the same footprint while using simplified 2D-like fabrication steps for each layer.
Solution Approach 2:
The patent segments the memory structure into multiple vertically stacked cells, each with its own source/drain regions and conductors. This segmentation allows independent fabrication of each cell layer using standard photolithography steps, enabling high integration density without requiring increasingly complex single-step fabrication processes.
Data Source
AI summary
A method of forming a memory structure includes the following steps. A CMOS circuitry is formed over a semiconductor substrate. A bit line array is formed to be electrically connected to the CMOS circuitry. A memory array is formed over the bit line array. The memory array is formed by forming a word line stack, and forming first and second sets of stacked memory cells. The word line stack is formed on the bit line array and has a first side surface and a second side surface. The first sets of stacked memory cells are formed along the first side surface. The second sets of stacked memory cells are formed along the second side surface, wherein the second sets of stacked memory cells are staggered from the first sets of stacked memory cells. A source line array is formed over the memory array and electrically connected to the CMOS circuitry.