3D Stacked Memory Cell Wiring for Lower-Cost High-Capacity DRAM
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Solution Overview
Problem
Existing dynamic random access memory (DRAM) technologies face challenges in reducing manufacturing costs while maintaining performance and efficiency, particularly in three-dimensionally stacked memory cells.
Innovation Solution
The memory device incorporates a three-dimensional structure with stacked memory cells, utilizing a plurality of layers arranged in a specific direction, connected by multiple wirings and transistors, and includes a sense circuit configuration that enhances data transfer and storage efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensionally stacked memory cells are used to increase storage capacity, then storage capacity is improved, but manufacturing complexity increases
Solution Approach 1:
The memory device is divided into multiple stacks, each containing multiple memory cells arranged in three dimensions. Each stack operates independently with its own bit lines and word lines, allowing parallel manufacturing and reducing overall complexity while increasing total storage capacity through the multiplication of stacks.
Solution Approach 2:
Memory cells are arranged in three-dimensional stacks rather than traditional two-dimensional planes. This vertical stacking increases storage capacity per unit area by utilizing the third dimension (height), allowing multiple memory cells to be stacked along the vertical axis while maintaining a compact footprint.
2Quantity of substance
If more wirings and transistors are added to support stacked memory cells, then storage capacity is improved, but device complexity increases
Solution Approach 1:
The bit lines and word lines are designed to serve multiple functions: they control multiple memory cells within a stack and can selectively access specific cells through coordinated activation. This multi-functionality reduces the need for dedicated control lines for each individual cell, thereby reducing overall wiring complexity while supporting increased storage capacity.
Solution Approach 2:
Transistors are introduced as intermediary switching elements between the bit lines, word lines, and memory cell capacitors. These transistors act as controlled gates that enable selective data access to specific memory cells, simplifying the control architecture by providing a standardized interface layer between control signals and storage elements.
3Ease of manufacture
If traditional two-dimensional DRAM structure is used, then manufacturing process is simpler, but storage capacity is limited
Solution Approach 1:
The invention transitions from two-dimensional memory cell arrangement to three-dimensional stacking. Memory cells are vertically stacked along the third dimension, allowing multiple layers of storage to be integrated within the same planar footprint. This dimensional transition dramatically increases storage capacity while maintaining compatibility with standard semiconductor manufacturing processes.
Solution Approach 2:
Multiple memory cells are nested vertically within stacked structures, with each cell layer containing capacitors, transistors, and interconnects arranged in repeating patterns. This nested configuration allows dense integration of storage elements in the vertical direction, achieving high storage capacity within a compact volume while using established fabrication techniques.
Data Source
AI summary
A memory device includes memory cells for each of layers arranged in a first direction, the memory cells of each layer including groups of memory cells, the memory cells of each group being arranged in a second direction intersecting the first direction, the groups being arranged in a third direction intersecting the first and second directions, first wirings arranged in the third direction in each layer and respectively connected to the groups in each layer, first transistors each connected to a corresponding first wiring, second wirings each connected to the first transistors of a corresponding layer, third wirings each extending in the first direction and connected to a memory cell in each layer, and fourth wirings each extending in the first direction and connected to a gate of a corresponding first transistor in each layer.