Stacked Memory Cells with Back Gates for Reduced Film Count
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Solution Overview
Problem
The increasing number of steps in manufacturing three-dimensional memory devices leads to extended production time, increased contamination risks, and decreased manufacturing yield due to the complexity of film formation, patterning, and heat treatment processes.
Innovation Solution
A memory device design that includes a circuit with stacked memory cells and transistors using oxide semiconductors, where the number of films and manufacturing steps is reduced, and the transistors have back gates to control threshold voltages and increase current flow, allowing for a more efficient and compact memory device structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional structure is employed for a memory device, then memory capacity and integration density are improved, but the number of manufacturing steps increases leading to extended production time and decreased manufacturing yield
Solution Approach 1:
The memory device is divided into multiple stacked memory cell layers, with each layer containing transistors and capacitors formed through sequential but simplified processing steps. This segmentation allows the complex three-dimensional structure to be built incrementally through manageable stages, reducing the overall complexity of each individual step while maintaining high integration density
Solution Approach 2:
The patent transitions from planar two-dimensional memory cell arrangement to a three-dimensional stacked configuration. Multiple memory cell layers are formed vertically stacked on top of each other, utilizing the vertical dimension to increase memory capacity without proportionally increasing the footprint area, thereby improving integration density while managing manufacturing complexity through standardized layer formation processes
2Quantity of substance
If a three-dimensional structure is employed for a memory device, then memory capacity is improved, but production time is extended due to increased number of steps
Solution Approach 1:
Common structural elements such as the substrate, lower gate electrodes, and insulating layers are formed in advance before the memory cell layers are stacked. This preliminary formation of shared components allows subsequent layers to be added more efficiently, reducing the cumulative production time required for the complete three-dimensional memory device
Solution Approach 2:
Multiple processing steps are merged into combined operations where possible. For example, the formation of gate electrodes and insulating layers is integrated across different memory cell layers using similar material deposition and patterning processes, reducing the total number of discrete steps and thereby decreasing overall production time
3Quantity of substance
If a three-dimensional structure is employed for a memory device, then memory capacity is improved, but manufacturing yield decreases due to increased contamination risks
Solution Approach 1:
The manufacturing process utilizes controlled environments with inert atmospheres during critical film formation and patterning steps. This protects the exposed surfaces and materials from contamination by moisture and oxygen, maintaining manufacturing yield while enabling the formation of complex stacked structures that would be more susceptible to contamination
Solution Approach 2:
Protective measures are implemented in advance during the manufacturing process, such as forming protective capping layers and using barrier films before subsequent processing steps. This beforehand cushioning prevents contamination from occurring in the first place, maintaining high manufacturing yield throughout the multi-step formation of the three-dimensional memory device
Data Source
AI summary
A memory device in which the number of films is reduced. The memory device includes a circuit and a wiring. The circuit includes a first memory cell and a second memory cell. The first memory cell includes a first transistor, a second transistor, and a first capacitor. The second memory cell includes a third transistor, a fourth transistor, and a second capacitor. The second memory cell is stacked over the first memory cell. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and the first capacitor. One of a source and a drain of the third transistor is electrically connected to a gate of the fourth transistor and the second capacitor. A gate of the first transistor and a gate of the third transistor are electrically connected to the wiring.