3D Semiconductor Memory Cell Stack Without Finer Lithography
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Solution Overview
Problem
The integration of two-dimensional semiconductor devices is limited by the cost and practicality of processing equipment needed to form fine patterns, leading to a need for three-dimensional semiconductor memory devices with increased integration capabilities.
Innovation Solution
A three-dimensional semiconductor memory device is designed with a stack structure comprising vertically stacked layers, including semiconductor patterns, conductive lines, and data storage elements, such as capacitors, to enhance integration and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor devices are used, then manufacturing simplicity is maintained, but integration density is limited
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cell layers are stacked along the vertical direction, with bit lines extending in the first direction and word lines extending in the second direction, enabling increased integration density by utilizing the third dimension for stacking multiple functional layers including semiconductor patterns, insulating layers, and conductive lines
2Quantity of substance
If processing equipment is upgraded to form finer patterns, then integration density improves, but manufacturing cost increases
Solution Approach 1:
Instead of relying on advanced lithography to reduce pattern dimensions, the patent achieves higher integration density by stacking multiple memory cell layers vertically. This approach maintains compatibility with existing manufacturing processes while increasing the number of memory cells per unit area through vertical stacking of semiconductor patterns, insulating layers, and conductive lines
3Quantity of substance
If three-dimensional stacked structure is implemented, then integration density increases, but device complexity increases
Solution Approach 1:
The three-dimensional memory structure is divided into multiple discrete layers including semiconductor patterns, first insulating layers, second insulating layers, and conductive lines. Each layer performs a specific function and can be manufactured using separate processing steps, allowing the complex three-dimensional structure to be built systematically through repeated stacking of standardized layer units
Solution Approach 2:
The stacked structure uses repeating units of semiconductor patterns, insulating layers, and conductive lines that serve multiple functions. The same layer configuration is repeated across multiple memory cell layers, with bit lines and word lines extending in different directions to access multiple memory cells, reducing the variety of unique components needed
Data Source
AI summary
A semiconductor memory device includes a stack structure including a plurality of layers vertically stacked on a substrate. Each of the plurality of layers includes a first dielectric layer, a semiconductor layer, and a second dielectric layer that are sequentially stacked, and a first conductive line in the second dielectric layer and extending in a first direction. The device also includes a second conductive line extending vertically through the stack structure, and a capacitor in the stack structure and spaced apart from the second conductive line. The semiconductor layer includes semiconductor patterns extending in a second direction intersecting the first direction between the first conductive line and the substrate. The second conductive line is between a pair of the semiconductor patterns adjacent to each other in the first direction. An end of each of the semiconductor patterns is electrically connected to a first electrode of the capacitor.