Stacked Memory Deck Assemblies for Precise Channel-Pillar Coupling
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Solution Overview
Problem
Existing methods for fabricating stacked memory decks face challenges in effectively coupling channel-material pillars, leading to inefficiencies in the formation of integrated assemblies.
Innovation Solution
A method involving the use of a 'soft' inter-deck material that is easily etched relative to other materials, allowing for precise formation of openings through stacked decks, followed by the deposition of memory cell materials within these openings, and subsequent replacement of sacrificial layers with conductive materials to create vertically stacked memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication methods are used to form stacked memory decks, then manufacturing process complexity increases, but manufacturing precision deteriorates due to difficulties in coupling channel-material pillars
Solution Approach 1:
The method performs preliminary actions by first forming sacrificial layers and inter-deck structures before forming the actual memory cell materials. The sacrificial layers are deposited and patterned in advance to define the positions where memory cell materials will later be formed, ensuring precise alignment and coupling of channel-material pillars across stacked decks.
Solution Approach 2:
The patent introduces inter-deck structures as intermediary elements between stacked memory decks. These inter-deck structures serve as mediators that facilitate the coupling of channel-material pillars across different decks, providing a structured interface that simplifies the integration process and improves coupling precision.
2Manufacturing precision
If openings are formed through stacked decks to deposit memory cell materials, then manufacturing precision improves for material placement, but device complexity increases due to additional fabrication steps
Solution Approach 1:
The fabrication process is segmented into distinct phases: first forming sacrificial layers and inter-deck structures, then forming openings, and finally depositing memory cell materials. This segmentation allows each step to be optimized independently, with the opening formation step specifically tailored to achieve precise material placement while maintaining overall process manageability.
3Manufacturing precision
If sacrificial layers are used to define opening positions, then manufacturing precision improves for opening formation, but loss of substance increases due to material removal
Solution Approach 1:
The patent employs sacrificial layers as temporary, disposable structures that are deposited, used to define opening positions, and then removed. These sacrificial layers serve their purpose precisely during the opening formation process and are subsequently eliminated, enabling high precision opening formation while accepting the temporary material addition and removal cycle.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the efficient fabrication of multi-deck memory devices with vertically aligned memory cells, improving the integration and performance of memory arrays by ensuring straight sidewalls and reducing fabrication complexities.
Implementation Method 1
The first material is removed from the region with an etch selective for the first material relative to the third and fourth materials
Implementation Method 2
deposition of memory cell materials within these openings
Data Source
AI summary
Some embodiments include an integrated assembly having a first deck which has first memory cells, and having a second deck which has second memory cells. The first memory cells have first control gate regions which include a first conductive material vertically between horizontally-extending bars of a second conductive material. The second memory cells have second control gate regions which include a fourth conductive material along an outer surface of a third conductive material. A pillar passes through the first and second decks. The pillar includes a dielectric-barrier material laterally surrounding a channel material. The first and fourth materials are directly against the dielectric-barrier material. Some embodiments include methods of forming integrated assemblies.


