Stacked Memory Channel Pairing for Scalable High-Speed Access
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Solution Overview
Problem
Existing two-dimensional integrated circuits (ICs) face limitations in efficiency and speed performance, especially for large data sets required by artificial neural networks, as they struggle to accommodate the exponential growth in processors and data sizes without significant increases in power consumption or latency.
Innovation Solution
The implementation of a 3D-IC structure with paired channels and a base die that facilitates flexible channel routing, allowing simultaneous or near-simultaneous access to multiple memory dies via cross-channel connections, without increasing the number of micro-bumps or vertical inter-stack connections, and includes a switching fabric with multiplexers and command decoders to manage signal routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If larger memories are implemented using traditional two-dimensional IC structures, then memory capacity increases, but efficiency and speed performance deteriorate
Solution Approach 1:
The patent transitions from two-dimensional IC layout to three-dimensional stacked architecture, where multiple memory dies are vertically stacked and connected through micro-bumps. This dimensional change enables significantly larger memory capacity while maintaining short access paths and high bandwidth, thereby preserving efficiency and speed performance despite increased capacity.
2Productivity
If the number of processors and data sets grows exponentially, then computing power increases, but power consumption and latency increase proportionally
Solution Approach 1:
By stacking memory dies vertically and connecting them through micro-bumps, the patent creates a three-dimensional memory architecture that provides exponential growth in memory capacity with linear or sub-linear growth in power consumption and latency. The vertical interconnects maintain short signal paths, preventing proportional increases in power and latency despite exponential scaling of computing resources.
3Speed
If more vertical inter-stack connections are added to increase memory access speed, then access speed improves, but device complexity increases
Solution Approach 1:
The patent divides the memory system into multiple independent dies stacked vertically, with each die containing a portion of the memory array. Cross-channel connections are established between corresponding channels of adjacent dies, creating a modular architecture that enables parallel access paths without requiring a complete redesign of the interconnect structure, thus managing complexity while improving access speed.
Solution Approach 2:
The cross-channel connections are designed to be multi-functional, serving both as data pathways and as part of the addressing mechanism. The base die's channel pairing logic can dynamically route signals through different vertical paths, allowing the same physical infrastructure to support multiple access patterns and reducing the need for dedicated interconnects for each function.
4Productivity
If channel routing is made flexible to enable simultaneous access to multiple memory dies, then memory access efficiency improves, but device complexity increases
Solution Approach 1:
The base die serves as an intermediary that manages cross-channel connections between vertically stacked memory dies. It contains the logic for pairing channels and routing signals dynamically, allowing simultaneous or near-simultaneous access to multiple dies without requiring complex control logic distributed across all dies. This centralized mediation simplifies the overall system complexity while enabling flexible, efficient access patterns.
Data Source
AI summary
A stacked memory device includes memory dies over a base die. The base die includes separate memory channels to the different dies and external channels that allow an external processor access to the memory channels. The base die allows the external processor to access multiple memory channels using more than one external channel. The base die also allows the external processor to communicate through the memory device via the external channels, bypassing the memory channels internal to the device. This bypass functionality allows the external processor to connect to additional stacked memory devices.