Stacked Memory Cell Isolation Through Segmented Charge Traps
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Solution Overview
Problem
As the degree of integration of memory devices increases, interference between memory cells formed on different layers due to charge trap layers extending between them becomes significant, affecting program and read operations.
Innovation Solution
The implementation of interlayer insulating and conductive layers stacked alternately, with vertical holes and blocking layers to form a memory device structure that includes charge trap layers surrounded by blocking layers and a tunnel insulating layer, along with specific voltage application methods for program and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked vertically to increase integration degree, then storage capacity is improved, but interference between memory cells on different layers increases
Solution Approach 1:
The charge trap layer is segmented into separate regions for each memory cell by introducing blocking layers (first blocking layer and second blocking layer) that divide the continuous charge trap layer into isolated segments. This segmentation prevents charge leakage and interference between adjacent memory cells on different layers, enabling safe vertical stacking without compromising cell isolation.
Solution Approach 2:
Blocking layers are introduced as intermediary structures between adjacent charge trap layers on different layers. These blocking layers act as mediators that prevent direct charge transfer and interference between memory cells, while still allowing the vertical stacking architecture to maintain high integration density.
2Reliability
If blocking layers are added to suppress interference, then cell isolation is improved, but device complexity increases
Solution Approach 1:
The first blocking layer and second blocking layer are merged with the charge trap layer formation process, where both blocking layers and charge trap layers are formed in the same vertical stack sequence. This merging approach reduces the number of separate fabrication steps compared to forming blocking layers as distinct additional layers, thereby reducing manufacturing complexity while maintaining effective cell isolation.
Solution Approach 2:
Instead of adding blocking layers only in the horizontal plane, the solution extends isolation to the vertical dimension by forming blocking layers at different heights (first blocking layer below, second blocking layer above the charge trap layer). This three-dimensional isolation approach effectively suppresses interference while maintaining a compact structure that doesn't significantly increase overall device footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure effectively suppresses interference between memory cells, enhancing the reliability and efficiency of program and read operations by controlling electron transfer through precise voltage application.
Implementation Method 1
a tunnel insulating layer formed along inner walls of the second blocking layers and the charge trap layers
Data Source
AI summary
A memory device, and methods of manufacturing and operating the memory device, include alternately stacked interlayer insulating layers and conductive layers, a vertical hole configured to pass through the alternately stacked conductive layers and interlayer insulating layers, first blocking layers formed along the interlayer insulating layers exposed through the vertical hole, and second blocking layers formed along the conductive layers exposed through the vertical hole, with each second blocking layer having a thickness greater than that of each of the first blocking layers. The memory device also includes charge trap layers formed on the same layer as the interlayer insulating layers, and surrounded by the first and second blocking layers, a tunnel insulating layer formed along inner walls of the second blocking layers and the charge trap layers, and a channel layer formed along an inner wall of the tunnel insulating layer.