Stacked Memory Chip Package with Coupled Address Pads
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Solution Overview
Problem
Current multi-chip package devices face challenges in reducing size while maintaining or improving memory capacity and speed, particularly in cellular smartphones where smaller and lighter devices are required.
Innovation Solution
A novel multi-chip package device design featuring stacked memory chips with a memory region, peripheral circuits, and control circuits that include input/output pads for chip address programming, allowing for reduced size and efficient operation by coupling enable input and output pads between memory chips to successively input and manage chip addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory chips are stacked in a single package device, then memory capacity and speed are improved, but the size and weight of the package device increase
Solution Approach 1:
The patent transitions from horizontal arrangement of memory chips to vertical stacking configuration, utilizing the third dimension (height) to accommodate multiple chips. This dimensional change allows multiple memory chips to be integrated in a compact footprint, improving memory capacity while minimizing the increase in package device volume.
Solution Approach 2:
The patent implements a nested structure where multiple memory chips are stacked one on top of another within a single package device. Each memory chip is positioned vertically above the previous one, creating a compact nested arrangement that maximizes space utilization and reduces the overall package size compared to horizontal placement.
2Speed
If multiple memory chips are stacked in a single package device, then memory speed is improved, but the complexity of address management increases
Solution Approach 1:
The patent divides the address management function into segments, with each memory chip having dedicated input/output pads for receiving chip addresses. The address bus is segmented to selectively activate specific memory chips based on their unique addresses, simplifying the overall address management by distributing the control logic across individual chips rather than requiring centralized complex management.
Solution Approach 2:
The patent introduces enable input pads and enable output pads as intermediary elements that facilitate address management between the controller and multiple memory chips. These intermediary pads act as gatekeepers that selectively enable or disable memory chip access based on address matching, simplifying the address management process by providing a standardized interface for chip selection.
Data Source
AI summary
Provided herein may be a memory chip, a package device having the memory chip, and a method of operating the package device. The memory chip comprising a plurality of memory blocks each including a plurality of memory cells for storing data; a plurality of input/output pads to which a chip address is inputted; and a plurality of peripheral circuits configured to program the chip address to a selected memory block among the memory blocks.