Stacked Memory Chip Data Protection via Cross-Chip ECC Distribution
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Solution Overview
Problem
Stacked DRAM devices, such as those conforming to HBM2 and HBM3 standards, lack the splitting of cache lines into multiple pieces for error protection, making them prone to complete data loss if a 'bad chip' fails, exceeding the error threshold beyond which data recovery is not possible.
Innovation Solution
Implementing mirroring and ECC protection schemes across multiple memory chips within a stacked memory device, where cache line data is duplicated at various granularities (row/column, bank, pseudo-channel, channel) and ECC information is distributed across different chips, ensuring redundancy and error correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If cache line data is stored in a single memory chip, then storage capacity is maximized, but complete data loss occurs if the chip fails
Solution Approach 1:
The cache line is segmented into multiple pieces and distributed across different memory chips. Each piece is stored in a separate chip, so that if one chip fails, the data can still be recovered from the remaining chips. This segmentation resolves the contradiction by trading some storage efficiency for improved reliability through spatial distribution of data.
Solution Approach 2:
Redundant copies of cache line pieces are created and stored across multiple memory chips. The system maintains multiple copies of data fragments in different chips, enabling recovery from chip failures. This copying mechanism allows the system to tolerate chip failures while maintaining data integrity.
2Reliability
If cache line data is split across multiple memory chips, then error recovery capability is improved, but storage efficiency decreases
Solution Approach 1:
Instead of splitting all data uniformly across multiple chips, the system applies partial splitting only where necessary for error recovery. The degree of splitting is optimized to provide sufficient redundancy for recovery while minimizing the impact on storage efficiency. This partial action approach balances reliability improvement with productivity maintenance.
Data Source
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AI summary
A stacked memory chip device is described. The stacked memory chip device includes a plurality of stacked memory chips. The stacked memory chip device includes read/write logic circuitry to service read/write requests for cache lines kept within the plurality of stacked memory chips. The stacked memory chip device includes data protection circuitry to store information to protect substantive data of cache lines in the plurality of stacked memory chips, where, the information is kept in more than one of the plurality of stacked memory chips, and where, any subset of the information that protects respective substantive information of a particular one of the cache lines is not stored in a same memory chip with the respective substantive information.