3D Stacked Memory Chip Interconnects for Higher Storage Density
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently integrating and increasing capacity while maintaining data storage reliability and performance.
Innovation Solution
A semiconductor memory device with a three-dimensional memory structure, featuring a stacked interconnect configuration and a memory cell array with memory pillars and bit lines, enhances integration and capacity by utilizing a source line, word lines, and select transistors to improve data storage efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional memory structure is adopted to enhance integration and increase capacity, then storage capacity and integration density are improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The memory device is divided into multiple chips (first chip and second chip) stacked together, with each chip containing specific functional regions (memory cell array, circuit regions). This segmentation allows complex 3D functionality to be distributed across modular units, improving manufacturability while maintaining high storage capacity.
Solution Approach 2:
The patent transitions from planar 2D memory architecture to a 3D stacked architecture where memory cells are arranged vertically across multiple chips. Memory pillars extend in the vertical direction, and chips are stacked along the thickness direction, utilizing the third dimension to dramatically increase storage capacity without proportionally increasing footprint area.
2Quantity of substance
If multiple chips are stacked to increase capacity, then storage density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The memory device is divided into multiple chips (first chip and second chip) stacked together, with each chip containing specific functional regions (memory cell array, circuit regions). This segmentation allows complex 3D functionality to be distributed across modular units, improving manufacturability while maintaining high storage capacity.
Solution Approach 2:
Connection pads are introduced as intermediary elements between the first chip and second chip, providing electrical connection interfaces that facilitate precise alignment and bonding. These connection pads act as mediators that enable reliable inter-chip connectivity while accommodating manufacturing tolerances.
3Device complexity
If a stacked interconnect configuration is used to improve integration, then device complexity increases, but electrical connection reliability must be maintained
Solution Approach 1:
The memory device is divided into multiple chips (first chip and second chip) stacked together, with each chip containing specific functional regions (memory cell array, circuit regions). This segmentation allows complex 3D functionality to be distributed across modular units, improving manufacturability while maintaining high storage capacity.
Solution Approach 2:
Connection pads are introduced as intermediary elements between the first chip and second chip, providing electrical connection interfaces that facilitate precise alignment and bonding. These connection pads act as mediators that enable reliable inter-chip connectivity while accommodating manufacturing tolerances.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes: a first chip including a substrate defining a first region and a second region; and a second chip contacting the first chip in a first direction, the second chip being electrically connected to the first chip via a plurality of connection pads at a boundary region. The second chip includes a memory cell array, the memory cell array including a source line, word lines below the source line, and a memory pillar. The second chip further includes contacts extending in the first direction and each electrically connected to one of the connection pads, a conductor pattern contacting upper ends of the contacts, and a first interconnect extending above the conductor pattern and electrically connected to the conductor pattern.