Stacked Memory Die Layout for Chip-Kill Data Protection
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Solution Overview
Problem
Current memory systems face challenges in ensuring data protection and recovery when a constituent chip in a stack of memory dice fails, leading to potential single points of failure and data integrity issues during read and write operations.
Innovation Solution
The implementation of a 'chip kill' mechanism using Compute Express Link (CXL) compliant memory systems, which distributes error correction information across memory dice, allowing the system to maintain functionality even if one chip fails, by utilizing Compute Express Link (CXL) protocols and PCIe interfaces for managing host interfaces and error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction information is concentrated in a single memory die, then the memory system structure is simpler, but the system becomes vulnerable to single points of failure
Solution Approach 1:
The patent divides error correction information into multiple segments and distributes them across different memory dice within the stack. Each memory die stores a portion of the error correction code, so that no single point of failure can compromise the entire error correction capability. This segmentation approach maintains reliability while managing complexity through structured distribution.
Solution Approach 2:
The patent implements a hierarchical nesting structure where error correction information is embedded within the memory stack architecture. The error correction codes are nested across multiple memory dice, with each die containing both data and portions of error correction information. This nested arrangement allows the system to maintain functionality even when individual components fail.
2Reliability
If error correction information is distributed across multiple memory dice, then the system becomes more resilient to chip failures, but the memory system structure becomes more complex
Solution Approach 1:
The patent segments error correction information across multiple memory dice, with each die holding a specific portion of the error correction code. This segmentation distributes the resilience function across the stack, ensuring that failure of any single die does not compromise the entire system's error correction capability.
Solution Approach 2:
The patent extends the error correction architecture into the vertical dimension of the memory stack. Instead of horizontal distribution only, error correction information is distributed across multiple layers or levels of the stacked memory architecture, utilizing the third dimension to achieve redundancy and resilience while managing complexity through spatial organization.
3Reliability
If traditional memory architectures are used without chip kill mechanisms, then the device complexity is lower, but data protection and recovery capabilities are insufficient
Solution Approach 1:
The patent implements preliminary error correction by pre-distributing error correction information across memory dice before any failures occur. The chip kill mechanism is pre-configured with distributed error correction codes, enabling automatic detection and correction of failures without requiring complex real-time decision-making during operation.
Solution Approach 2:
The patent introduces error correction information as an intermediary element that mediates between the stored data and potential failures. This intermediary layer of error correction codes acts as a buffer, allowing the system to recover from failures without directly exposing the complexity of the recovery mechanisms to the host system.
4Speed
If high-speed data transfer protocols like CXL are implemented, then data transfer speed improves, but the system requires more sophisticated error correction mechanisms
Solution Approach 1:
The patent segments error correction processing across multiple memory dice, allowing parallel error correction operations to occur simultaneously. This segmentation enables high-speed data transfer by distributing the error correction workload, preventing any single bottleneck from limiting overall system performance.
Solution Approach 2:
The patent implements self-service error correction where each memory die autonomously handles its own error correction using locally stored error correction information. This self-service approach eliminates the need for complex centralized error correction mechanisms, reducing overall system complexity while maintaining high-speed data transfer capabilities.
Data Source
AI summary
Some memory dice in a stack can be connected externally to the stack and other memory dice in the stack can be connected internally to the stack. The memory dice that are connected externally can act as interface dice for other memory dice that are connected internally thereto. Data protection and recovery schemes provided for the stacks of memory dice can be based on data that are transferred in a single data stream without a discontinuity between those data transfers from the memory dice of the stacks.