Stacked Memory Chip Layout With Merged Address and Chip Selection
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Solution Overview
Problem
Semiconductor memory devices face challenges in reducing manufacturing costs.
Innovation Solution
The semiconductor memory device is configured with a core chip group comprising serially-coupled core chips, each with specific terminal and logic circuit arrangements, and a multi-layered structure that allows efficient signal communication and integration, reducing manufacturing complexity and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If a conventional storage device structure is used, then the device can store data, but the device consumes more power and generates more heat due to redundant circuitry for address decoding and chip selection
Solution Approach 1:
The patent combines the address decoding function and chip selection function into a single integrated circuit structure. The address decoder simultaneously performs both address decoding and chip selection based on the same decoded address signals, eliminating the need for separate chip selection circuitry and reducing overall power consumption while maintaining data storage functionality
2Temperature
If a conventional storage device structure is used, then the device can store data, but the device generates more heat due to redundant circuit operations
Solution Approach 1:
The patent merges the address decoding operation and chip selection operation into a single simultaneous process within the integrated circuit. By using the same decoded address signals for both functions, the circuit performs fewer separate operations, reducing heat generation while maintaining data storage capability
3Loss of time
If a conventional storage device structure is used, then the device can store data, but the device takes more time to decode addresses and select chips
Solution Approach 1:
The patent integrates address decoding and chip selection into a single simultaneous operation within the same circuit block. The address decoder generates decoded signals that are directly used for chip selection without requiring a separate chip selection decoding stage, thereby reducing the total time required for address decoding and chip selection while maintaining data storage functionality
Data Source
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AI summary
A semiconductor memory device includes a first and second substrates; and a first and second element layers respectively provided on an upper surface of the first and the second substrates. The first and second substrates respectively include a first and second vias. The first and second element layers respectively includes a first and second pads respectively electrically coupled to the first and second vias, and respectively provided on an upper surface of the first and second element layers. The upper surface of the second element layer is arranged so as to be opposed to the upper surface of the first element layer. The first and second pads are electrically coupled and symmetrically arranged with respect to a surface where the first and second element layers are opposed to each other.