Stacked Memory Chip Noise Reduction via Segmentation
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Solution Overview
Problem
Memory devices face noise issues due to voltage drops caused by resistance, which affect integration density and performance.
Innovation Solution
A memory device design with a stacked chip configuration, where the memory cell array is in the upper chip and at least a portion of the row decoder and common source line driver are in the lower chip, connected via bonding pads to reduce resistance and noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the memory cell array and common source line driver are integrated in the same chip, then the integration density is improved, but the resistance increases causing voltage drops and noise
Solution Approach 1:
The memory device is divided into two separate chips: the upper chip contains the memory cell array while the lower chip contains the common source line driver. This segmentation reduces the resistance in the electrical path between these components, thereby minimizing voltage drops and noise while maintaining high integration density through the stacked configuration.
2Object-affected harmful factors
If the electrical path between memory cell array and common source line driver is lengthened, then the resistance is reduced, but the device area increases
Solution Approach 1:
The patent transitions from a planar layout to a three-dimensional stacked configuration. By placing the memory cell array in the upper chip and the common source line driver in the lower chip, the electrical path is optimized vertically rather than horizontally, reducing resistance without increasing the footprint area of the device.
3Object-affected harmful factors
If bonding pads are used to connect upper and lower chips, then the resistance is reduced, but the manufacturing complexity increases
Solution Approach 1:
The use of bonding pads to connect the upper and lower chips is a standard semiconductor packaging technique. While it adds some manufacturing steps, the benefits of reduced resistance and noise outweigh the moderate increase in manufacturing complexity, as bonding pad technology is well-established in the industry.
Data Source
AI summary
A memory device includes a memory cell array, a row decoder connected to the memory cell array by a plurality of string selection lines, a plurality of word lines, and a plurality of ground selection lines, and a common source line driver connected to the memory cell array by a common source line. The memory cell array is located in an upper chip, at least a portion of the row decoder is located in a lower chip, at least a portion of the common source line driver is located in the upper chip, and a plurality of upper bonding pads of the upper chip are connected to a plurality of lower bonding pads of the lower chip to connect the upper chip to the lower chip.