3D Stacked Memory Chip Layout With TSVs and On-Chip NPU
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Solution Overview
Problem
Current memory chips face challenges in increasing integration density and performance due to limited chip space, necessitating innovative stacking and connectivity solutions for enhanced functionality.
Innovation Solution
A memory chip design featuring vertically stacked cell and core-periphery chips, connected via through-silicon vias (TSVs), with neural processing units (NPUs) and optimized regional arrangements for improved data processing speed and integration density, allowing for efficient data operations and reduced noise and heat generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more circuits are formed on a limited chip region, then integration density is improved, but chip area increases
Solution Approach 1:
The patent transitions from planar 2D circuit arrangement to 3D vertical stacking by forming cell chips and core-periphery chips in separate layers and connecting them through TSVs. This dimensional change allows circuits to be distributed across multiple vertical levels, increasing integration density without expanding the horizontal chip footprint.
Solution Approach 2:
The memory chip is segmented into functionally distinct cell chips (containing memory cells) and core-periphery chips (containing core and peripheral circuits). This segmentation allows independent optimization of each chip type and enables vertical stacking, thereby increasing overall integration density while maintaining manageable chip dimensions.
2Ease of manufacture
If cell regions, core regions, and peripheral regions are arranged in a planar layout, then manufacturing is simplified, but data transmission distance increases
Solution Approach 1:
The patent relocates cell regions to a different vertical layer (cell chip) while keeping core and peripheral regions on the core-periphery chip. This vertical separation reduces the horizontal data transmission distance between these functional regions while maintaining planar manufacturing simplicity within each individual chip layer.
3Quantity of substance
If circuits are densely packed in a planar configuration, then integration density improves, but noise and heat generation increase
Solution Approach 1:
By distributing circuits across multiple vertical layers through chip stacking, the patent increases the physical separation between adjacent circuits. This vertical spacing reduces electromagnetic interference (noise) and improves heat dissipation while maintaining high integration density through the multi-layer architecture.
Data Source
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AI summary
A memory chip includes a cell chip and a core-periphery chip, which are vertically stacked and are electrically connected to each other. The cell chip includes cell regions, each of which includes a memory cell layer. The core-periphery chip includes a core group region and a peripheral region which are adjacent to each other in a first direction. The core group region includes core regions arranged in a line in a second direction intersecting the first direction. Each of the core regions includes a core bank including a core circuit, and a neural processing unit (NPU) block including an NPU.