Stacked Memory Chip With Rewiring Lines For Wire Coupling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge is to reduce the size and thickness of semiconductor devices while enabling efficient mounting of a microcomputer chip and multiple memory chips on a single semiconductor device, while also allowing for easy electrical coupling between the microcomputer chip and memory chips, as well as between the external LSI and the microcomputer chip.
Innovation Solution
The solution involves a stacked configuration where memory chips with pads along two opposed sides have lead-out wiring lines that expose hidden pads from the lower memory chip, allowing wire coupling without a spacer, and the microcomputer chip is mounted such that its electrodes are coupled with the memory chip pads through wires, facilitating reduced size and thickness by eliminating spacer intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If semiconductor chips are simply stacked to reduce planar area, then the area is reduced, but the pads on the lower-stage chip are covered and wire coupling becomes difficult
Solution Approach 1:
The pad arrangement transitions from a single-plane configuration to a multi-dimensional configuration by placing pads on both the main surface and the side surface of the memory chip. This allows wire coupling to access pads from multiple spatial dimensions, solving the coverage problem when chips are stacked.
Solution Approach 2:
The pad group is segmented into multiple subsets: pads on the main surface, pads on the side surface, and exposed pads from the lower-stage chip. This segmentation allows different portions of the electrical connection to be established through different spatial paths, enabling wire coupling without requiring large spacers.
2Ease of manufacture
If a spacer is interposed between chips to ensure wire bonding space, then wire coupling becomes possible, but the height of the semiconductor device becomes larger
Solution Approach 1:
Instead of increasing the vertical dimension (thickness) with a spacer, the solution utilizes the side surface dimension of the memory chip to position pads. This allows wire coupling to occur in a different spatial dimension, avoiding the need for increased device thickness.
Solution Approach 2:
The pad distribution is optimized locally by placing pads on the side surface at positions that are easily accessible for wire coupling. This local optimization of pad positioning eliminates the need for global structural modifications like spacers.
3Productivity
If pads are arranged along plural sides of the memory chip for better wiring distribution, then wiring distribution is improved, but the device complexity increases
Solution Approach 1:
The side surface of the memory chip serves multiple functions: it provides mechanical support, defines the chip boundary, and hosts functional pads for electrical connection. This multi-functionality improves wiring distribution without adding separate structural elements that would increase complexity.
Data Source
AI summary
A semiconductor device with semiconductor chips stacked thereon is provided. The semiconductor device is reduced in size and thickness. In a first memory chip and a second memory chip, first pads of the first memory chip located at a lower stage and hidden by the second memory chip located at an upper stage are drawn out by re-wiring lines, whereby the first pads projected and exposed from the overlying second memory chip and second pads of the second memory chip can be coupled together through wires. Further, a microcomputer chip and third pads formed on re-wiring lines are coupled together through wires over the second memory chip, whereby wire coupling of the stacked memory chips can be done without intervention of a spacer.