Stacked Memory Chip Package Stitch Orientation for Area Reduction
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Solution Overview
Problem
Conventional semiconductor package designs face challenges in reducing package size when stacking multiple chips due to complex wiring and increased space requirements to prevent wire intersections, leading to larger package areas.
Innovation Solution
The design involves arranging chip select pads on the ends of electrode pad lines, with stitches formed in different directions to reduce connection distances and prevent wire intersections, allowing for a more compact layout by minimizing the space needed to avoid wire contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple chips are stacked on top of each other with conventional wiring arrangements, then chip capacity and integration are improved, but package area increases due to complex wiring and space required to prevent wire intersections
Solution Approach 1:
The patent applies dimensionality change by arranging stitches in different directions (first direction and second direction perpendicular to the first) on the mounting board. This directional organization allows wires connecting to stitches in different directions to naturally avoid intersections, reducing the space required to prevent wire contact while maintaining high chip stacking capacity
Solution Approach 2:
The patent segments the electrode pads into two distinct groups: chip select pads connected to stitches in a first direction, and other pads connected to stitches in a second direction perpendicular to the first. This segmentation organizes the wiring layout, reduces complexity, and minimizes the package area by preventing wire intersections through directional separation
2Ease of manufacture
If chip select pads are arranged along with other electrode pads in the same line, then manufacturing is simplified, but package area increases due to longer connection distances and more complex wiring
Solution Approach 1:
The patent segments electrode pads into two functional groups arranged in different directions: chip select pads in a first direction and other pads in a second direction. This segmentation reduces connection distances for each group, simplifies wiring by preventing intersections, and decreases package area while maintaining ease of manufacture through systematic organization
Solution Approach 2:
The patent employs asymmetric arrangement by positioning chip select pads and other pads in different directional orientations rather than symmetrically along the same line. This asymmetric layout optimizes connection distances, reduces wiring complexity, and minimizes package area by exploiting the functional differences between chip select and other pads
3Device complexity
If stitches are arranged in a single line to connect all electrode pads, then device complexity is reduced, but wire intersections occur requiring larger space to prevent contact
Solution Approach 1:
The patent transitions from a single-line stitch arrangement to a two-dimensional grid arrangement where stitches are organized in both a first direction and a second direction perpendicular to the first. This dimensional expansion reduces device complexity by providing clear directional organization while simultaneously preventing wire intersections through the perpendicular arrangement, reducing the space needed to prevent contact
Data Source
AI summary
A first memory chip (103a) and a second memory chip (103b) mounted in this order on one surface of a mounting board (101) each have a rectangular planar shape and include a plurality of electrode pads formed in a single line along one side of the rectangle. An electrode pad line of the second memory chip (103b) is formed in parallel with an electrode pad line of the first memory chip (103a). A chip select pad is disposed on an end of the electrode pad line. Control pads, address pads, or data pads (113a) of the first memory chip (103a) are wire bonded to first stitches (109) formed in a single line along one side of the rectangle. A chip select pad (121a) and a chip select pad (121b) are wire bonded to second stitches (111) formed in a line along a side adjacent to a side of the chip select pad (121a). Accordingly, an increase in package area is suppressed when a plurality of memory chips are stacked.