3D Stacked Semiconductor Memory Chip Structure for Higher Integration
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Solution Overview
Problem
Current semiconductor memory devices face limitations in increasing integration density due to the need for expensive miniaturization equipment and the demand for higher functionality, speed, and miniaturization in electronic components, which traditional two-dimensional designs struggle to meet.
Innovation Solution
A semiconductor memory device design featuring stacked semiconductor chips with a substrate attachment film that connects the chips, allowing for improved integration and reliability by using a mold structure with gate electrodes and channel structures, and contact vias for efficient electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional planar semiconductor memory devices are used, then manufacturing is simpler, but integration density is limited
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory chips. Multiple memory chips are stacked in the vertical direction and interconnected through through-silicon vias (TSVs) and substrate attachment films, enabling significantly higher integration density while maintaining manufacturing feasibility through established 3D stacking processes.
2Quantity of substance
If ultra-fine pattern forming technology is used to increase integration density, then more memory cells fit in the same area, but expensive apparatuses are required
Solution Approach 1:
Instead of continuing to shrink pattern sizes in the two-dimensional plane which requires increasingly complex and expensive lithography equipment, the patent stacks multiple complete memory chip layers vertically. This 3D stacking approach achieves higher integration density using standard fabrication processes without requiring ultra-fine pattern forming apparatus.
Solution Approach 2:
The memory device is divided into multiple separate memory chips that are fabricated independently using standard processes, then stacked and interconnected. Each chip can be manufactured using conventional equipment, avoiding the need for ultra-fine pattern forming apparatus while achieving high overall integration density through the stacked configuration.
3Quantity of substance
If multiple semiconductor chips are stacked, then integration density increases, but design complexity increases
Solution Approach 1:
The patent employs standardized substrate attachment films and through-silicon via structures that serve multiple functions: mechanical bonding between chips, electrical interconnection, and signal routing. This universal interface design simplifies the overall system design despite the multi-chip configuration, as the same attachment and interconnection structures are reused across all chip stacks.
Data Source
AI summary
A semiconductor memory device comprising: a first semiconductor chip including an upper input/output pad, a second semiconductor chip including a lower input/output pad, and a substrate attachment film attaching the first and second semiconductor chips. The first and second semiconductor chips each include a first substrate including a first side facing the substrate attachment film and a second side, a mold structure including gate electrodes, a channel structure penetrating the mold structure and intersecting the gate electrodes, a second substrate including a third side facing the first side and a fourth side, a first circuit element on the third side of the second substrate, and a contact via penetrating the first substrate and connected to the first circuit element. The upper and lower input/output pads are on the second sides of the first and second semiconductor chip, respectively, and contact the contact vias of the first and second semiconductor chips.