Stacked Memory Chips Using Bank-Selective TSV Paths
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Solution Overview
Problem
The challenge in stacking multiple semiconductor memory chips is the limitation in increasing the number of electrodes connected to the package substrate, which restricts the number of memory chips that can be stacked due to the need for common electrical short-circuiting of through silicon vias, leading to increased wiring lengths and complexity in data transfer operations.
Innovation Solution
A semiconductor device with multiple memory chips stacked using through silicon vias, where each memory bank is activated differently to allow parallel data transfer via common penetration electrodes, reducing the need for extensive read/write buses and minimizing wiring lengths by distributing read data chip-by-chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If through silicon vias are electrically short-circuited to one another in the same planar positions, then the number of electrodes connected to the package substrate does not increase with the number of stacked memory chips, but the wiring lengths between memory banks and through silicon vias increase significantly
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked arrangement. Memory banks are distributed across multiple stacking directions (layers), allowing data transfer to occur vertically through short penetration electrodes rather than horizontally through long wiring paths. This dimensional change resolves the contradiction by making wiring length irrelevant to the number of stacked chips.
Solution Approach 2:
The patent divides the memory device into multiple independent memory banks distributed across different stacking directions. Each memory bank is associated with specific penetration electrodes, allowing parallel data transfer operations. This segmentation enables the system to handle increased storage capacity without proportionally increasing wiring complexity or length.
2Quantity of substance
If the data input/output width is extended by stacking memory chips, then the storage capacity increases, but the number of read/write buses required increases significantly
Solution Approach 1:
The penetration electrodes serve multiple functions: they act as data transfer pathways for multiple memory banks simultaneously, and they provide electrical connection across all stacked memory chips. This multi-functionality allows the same physical structure to support increased data input/output width without requiring additional dedicated buses for each function.
Solution Approach 2:
The patent implements dynamic selection of memory banks across different stacking directions based on access patterns. By activating different memory banks in different stacking directions, the system can achieve high data input/output width effectively utilizing the same penetration electrodes through time-multiplexed parallel operations, rather than requiring static dedicated buses for each potential data path.
Data Source
AI summary
A semiconductor device includes a stacked plurality of memory chips. The memory chips each include a plurality of memory banks, a plurality of read/write buses that are assigned to the respective memory banks, and a plurality of penetration electrodes that are assigned to the respective read/write buses and arranged through the memory chip. Penetration electrodes arranged in the same positions as seen in a stacking direction are connected in common between the chips. In response to an access request, the memory chips activate the memory banks that are arranged in respective different positions as seen in the stacking direction, whereby data is simultaneously input/output via the penetration electrodes that lie in different planar positions.