Stacked Memory Chiplet Coupling for Yield and Power Delivery
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Solution Overview
Problem
Memory systems with stacked semiconductor dies face low manufacturing yield due to the rejection of dies with a single failed component, and existing architectures do not efficiently manage power delivery, leading to reduced performance and increased latency.
Innovation Solution
The implementation of multiple semiconductor die portions, or chiplets, interconnected via conductive paths and through-silicon vias, with dedicated conductive paths for power delivery, forming a semiconductor unit that improves yield and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If monolithic semiconductor dies are used in stacked memory architectures, then manufacturing yield is reduced due to rejection of dies with single failed components, but device complexity is simplified
Solution Approach 1:
The patent divides a monolithic semiconductor die into multiple smaller die portions or chiplets. Each chiplet can be independently evaluated and manufactured, allowing partial yields to be utilized. Failed components in one chiplet do not necessitate rejection of the entire die structure, thereby improving manufacturing yield while managing complexity through modular design.
2Use of energy by moving object
If existing power delivery architectures are used in stacked memory, then power efficiency is reduced and latency increases, but device complexity is minimized
Solution Approach 1:
The patent implements dedicated conductive paths for power delivery to each chiplet, segmenting the power distribution network. This allows independent optimization of power delivery to each module, improving power efficiency and reducing latency by eliminating shared path contention, while the modular structure manages the inherent complexity.
Solution Approach 2:
The patent introduces through-silicon vias as intermediary structures that facilitate direct vertical power delivery between stacked chiplets. These vias act as dedicated conduits that bypass horizontal routing, reducing power delivery latency and improving efficiency by providing direct pathways through the substrate.
3Quantity of substance
If multiple chiplets are interconnected via conductive paths and through-silicon vias, then circuit density increases and manufacturing yield improves, but device complexity increases
Solution Approach 1:
The patent transitions from two-dimensional planar interconnection to three-dimensional vertical stacking with through-silicon vias. This dimensional change enables higher circuit density by utilizing the vertical axis for interconnections, allowing multiple chiplets to be stacked and interconnected in the thickness direction, thereby increasing the quantity of functional circuitry within a given footprint.
Data Source
AI summary
Methods, systems, and devices for techniques for semiconductor die coupling in stacked memory architectures are described. A semiconductor system may include a semiconductor unit formed by multiple semiconductor dies, where each semiconductor die may be fabricated to be individually separable. Each semiconductor die may include a respective portion of circuitry associated with the semiconductor unit. The multiple semiconductor dies may be coupled with a carrier, and each semiconductor die may be coupled (e.g., electrically, communicatively) with at least one other semiconductor die. At least some of the semiconductor dies may be coupled with a respective set of one or more memory arrays, where each memory array may be operable based on the coupling between the multiple semiconductor dies.