Stacked Memory Chiplet Package for Higher Yield Integration
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Solution Overview
Problem
The miniaturization of electronic packages leads to increased manufacturing difficulties and decreased yield due to the complexity of manufacturing processes, particularly when multiple transistors are integrated into a single chip, necessitating a more efficient and cost-effective method for integrating and interconnecting processing components and memory units.
Innovation Solution
An electronic package design that includes multiple processing components and memory units, where the memory units are stacked on the processing components and interconnected through bridging components, with solder-free joints to reduce manufacturing complexity and improve signal transmission efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple transistors are integrated into a single chip to increase processing power, then the functionality of the electronic package is improved, but the manufacturing difficulty increases and yield decreases
Solution Approach 1:
The patent divides a single complex processor into multiple separate processing components (chiplets) that can be manufactured independently at lower complexity levels. These chiplets are then integrated through a package interconnect architecture, allowing each component to be produced with higher yield while achieving the combined functionality of a single high-performance processor.
2Ease of manufacture
If a single chip is used to maintain manufacturing simplicity, then the manufacturing process is easier, but the processing power is limited
Solution Approach 1:
The processor is segmented into multiple chiplets that can be manufactured using simpler, more reliable processes. The package interconnect architecture then combines these chiplets to deliver the cumulative processing power equivalent to or exceeding a single high-performance chip, thereby achieving both manufacturing simplicity and high processing power.
Solution Approach 2:
The patent transitions from a two-dimensional single-chip architecture to a three-dimensional stacked architecture where multiple processing components and memory units are vertically integrated. This dimensional change enables increased processing power and memory capacity without proportionally increasing the footprint, while allowing independent fabrication of each layer.
3Device complexity
If processing components and memory are fabricated together on the same chip, then the integration is simpler, but the precision requirements increase and costs rise
Solution Approach 1:
The patent separates the fabrication of processing components and memory units into distinct manufacturing processes. Each component type can be optimized for its specific manufacturing requirements and produced at different fabrication nodes. The package interconnect architecture then integrates these separately fabricated components, reducing the precision requirements compared to monolithic integration while maintaining functional complexity.
4Quantity of substance
If memory units are stacked on processing components, then the memory capacity and access rate are improved, but the manufacturing complexity increases
Solution Approach 1:
The patent implements vertical stacking of memory units on processing components in the third dimension. This approach increases memory capacity and improves access rates by reducing the distance between processors and memory. The modular nature of the stack allows each layer to be independently fabricated and then vertically integrated through the package architecture, managing manufacturing complexity through standardization.
Solution Approach 2:
The package interconnect architecture serves as a universal interface that can accommodate different types of processing components and memory units. This standardized connection method simplifies manufacturing by allowing the same integration approach to be used across various component configurations, reducing the overall manufacturing complexity despite the increased device functionality.
Data Source
AI summary
An electronic package is provided. The electronic package includes a first processing component, a second processing component, and a first memory unit. The first memory unit is over the first processing component and the second processing component. The first processing component and the second processing component are configured to access data stored in the first memory unit.