Stacked Memory Read Clock Alignment Using Core Die Delay Paths
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Solution Overview
Problem
In stacked semiconductor memory devices, the varying distances and temperatures of core dies from the interface die lead to inconsistent propagation times for data and commands, causing timing misalignment during read and write operations, which existing alignment circuits fail to adequately address.
Innovation Solution
The implementation of a read clock timing alignment system where each core die includes a delay circuit that delays the read clock and returns it to the interface die, allowing the data latch to synchronize with the specific propagation delays of each core die, using a replica path to measure and adjust delays for precise timing alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If data aligners are used to add delays to ensure data alignment from different core dice, then timing alignment is improved, but device complexity increases
Solution Approach 1:
The patent creates a replica path that copies the essential timing characteristics of the native path without including all the complexity of the actual data path. The replica path contains delay circuits and alignment circuits that replicate the timing behavior, allowing delay measurement without requiring the full complexity of the native data path to be duplicated for measurement purposes.
Solution Approach 2:
The patent divides the timing alignment system into separate functional segments: the native path for actual data transmission, the replica path for delay measurement, and control circuits for adjusting delays. This segmentation allows the complex timing alignment function to be broken into manageable parts that can be independently optimized and controlled.
2Measurement precision
If individual delay circuits are implemented in each core die to account for propagation delays, then timing precision is improved, but manufacturing complexity increases
Solution Approach 1:
The patent implements universal delay circuits and alignment circuits that can be replicated across multiple core dice with the same design. These circuits serve multiple functions: they delay signals, they enable delay measurement through the replica path, and they can be controlled by centralized control logic. This multi-functionality reduces the need for custom-designed circuits for each core die.
Solution Approach 2:
The patent uses controllable delay circuits whose delay parameters can be adjusted based on measured propagation times. Rather than requiring precisely manufactured fixed delays, the system measures actual propagation delays and programmatically adjusts the delay circuit parameters to achieve proper timing alignment, compensating for manufacturing variations.
3Manufacturing precision
If replica paths are used to measure and adjust delays, then timing alignment accuracy is improved, but device complexity increases
Solution Approach 1:
The replica path creates a simplified copy of the native path that captures the essential timing characteristics without duplicating all the functional complexity. The replica path includes delay circuits and alignment circuits that mirror the timing behavior of the native path, enabling accurate delay measurement while maintaining a simpler measurement path.
Solution Approach 2:
The replica path acts as an intermediary between the actual data path and the control system. Instead of directly measuring delays in the complex native path, the control system uses the replica path as a mediator to indirectly measure and adjust timing parameters, simplifying the control process while maintaining accuracy.
Data Source
AI summary
Apparatuses, systems, and methods for read clock timing alignment in a stacked memory. An interface die provides a read clock to a core die. The core die includes a serializer which generates data with timing based on the read clock and an adjustable delay circuit which provides a delayed read clock back to the interface die. The interface die outputs the data with timing based on the delayed read clock received from the core die. In this way, the read clock passes along a return clock path from the interface die, through a delay circuit of the core die and back to the interface die before controlling data output timing. Each core die may adjust the timing of the delay of the read clock in order to better align the read clock with the timing of data provided from that die.