3D Stacked Memory Clock Division for Signal Integrity
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Solution Overview
Problem
As memory devices increase in clock frequency and stack height, transmitting clock frequency becomes difficult and unreliable due to capacitance, resistance, and inductance on inter-die lines, leading to signal integrity issues and high power consumption.
Innovation Solution
Dividing the clock frequency in the primary memory die to send a divided clock to internal memory dies via inter-die interconnects, improving signal integrity and reducing power consumption by toggling at a lower frequency, which also allows for faster operation in larger 3D stacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the clock frequency is increased to achieve faster memory operation, then the memory speed improves, but the signal integrity deteriorates due to capacitance, resistance, and inductance on inter-die lines
Solution Approach 1:
The clock signal transmission path is segmented into multiple independent paths: a first clock path for transmitting the clock signal from the first die to the second die, and a second clock path for transmitting a divided clock signal from the second die to the third die. This segmentation isolates the high-frequency clock signal to only the first inter-die connection, reducing the cumulative effect of capacitance, resistance, and inductance across multiple dies while maintaining fast operation speeds.
2Speed
If the clock frequency is increased to achieve faster memory operation, then the memory speed improves, but the power consumption increases due to higher frequency toggling on inter-die lines
Solution Approach 1:
The clock distribution network is segmented such that only the first clock path operates at the full high-frequency clock signal, while the second clock path operates at a divided lower frequency. This reduces the dynamic power consumption (proportional to frequency) on the longer inter-die connection between the second and third dies, while maintaining fast operation through the critical first clock path.
Solution Approach 2:
The clock frequency parameter is changed locally at the second die by dividing the incoming high-frequency clock signal to generate a lower-frequency divided clock signal for transmission to the third die. This parameter change reduces power consumption on the second inter-die connection while the first connection maintains the high frequency needed for fast operation.
3Quantity of substance
If the stack height is increased to achieve higher memory density, then the memory capacity improves, but the clock signal transmission becomes more difficult and unreliable due to accumulated inter-die line parasitics
Solution Approach 1:
The clock transmission system is segmented into hierarchical levels: the first die transmits the full-frequency clock to the second die, and the second die transmits a divided lower-frequency clock to the third die. This segmentation reduces the cumulative parasitic effects (capacitance, resistance, inductance) on each individual inter-die connection, enabling reliable clock distribution across taller stacks with more dies while maintaining high memory density.
Data Source
AI summary
A memory device includes a substrate with two or more memory die stacked in a three-dimensional stacked (3DS) configuration. The memory device includes a clock input configured to receive a clock from a host device. The memory device also includes a command input configured to receive command and address bits from the host device. The two or more memory die each include its own plurality of memory cells. Furthermore, each of the two or more memory die include a local control circuitry configured to receive or transmit a divided clock that is based on the clock.