Stacked Memory Clock Enable via Command Decoding
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Solution Overview
Problem
In semiconductor memory devices, the alignment of internal control signals with clock signals is challenging due to manufacturing variations, voltage, temperature, and decoder performance, leading to potential errors and reduced performance, especially in stacked memory devices without a clock enable pin.
Innovation Solution
The semiconductor memory device employs an interface semiconductor die and a memory semiconductor die connected via through-silicon vias, where the interface die generates an interface clock enable signal and the memory die generates a memory clock enable signal based on power mode commands, eliminating the need for a clock enable pin and enabling independent decoding of command signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a clock enable pin is used to control clock supply in stacked memory devices, then clock timing control is simplified, but device complexity and pin count increase
Solution Approach 1:
The patent extracts the clock enable function from a dedicated pin and relocates it to be generated internally by the command decoder circuit. This eliminates the need for an external clock enable pin while maintaining the timing control function, thereby reducing device complexity and pin count.
Solution Approach 2:
The command decoder circuit is given multiple functions: it decodes command signals and simultaneously generates the clock enable signal. This multi-functionality approach eliminates the need for a separate clock enable pin, reducing overall device complexity while maintaining operational capability.
2Ease of operation
If command signals are decoded at the interface die, then signal processing is simplified, but signal synchronization between stacked dies deteriorates
Solution Approach 1:
The interface die performs preliminary decoding of command signals before transferring them to the memory die. This preliminary action allows the memory die to receive pre-decoded signals, reducing the decoding burden and improving synchronization reliability between stacked dies.
Solution Approach 2:
The decoding function is segmented and distributed: the interface die handles initial command decoding, while the memory die performs additional decoding. This segmentation allows each die to handle specific decoding tasks, improving overall signal synchronization and processing efficiency.
3Reliability
If additional circuitry is added to improve signal alignment, then signal synchronization improves, but device size and complexity increase
Solution Approach 1:
The patent merges the clock enable signal generation function into the existing command decoder circuit. This integration eliminates the need for separate additional circuitry to generate clock enable signals, improving signal alignment while avoiding increases in device complexity.
Data Source
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AI summary
A semiconductor memory device includes an interface semiconductor die, a memory semiconductor die, and through-silicon vias connecting the interface semiconductor die and the memory semiconductor die. The interface semiconductor die includes a plurality of command pins to receive command signals transferred from a memory controller and an interface command decoder to decode the command signals. The memory semiconductor die includes a memory integrated circuit configured to store data and a memory command decoder to decode the command signals transferred from the interface semiconductor die. The interface semiconductor die does not include a clock enable pin to receive a clock enable signal from the memory controller. The interface and memory command decoders generate interface and memory clock enable signals to control respectively control a first and a second clock supply with respect to the interface and memory semiconductor dies, based on a power mode command transferred through the plurality of command pins from the memory controller and the plurality of through-silicon vias from the interface semiconductor die.