Stacked Semiconductor Memory Layout for Smaller CMOS Chip Area
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Solution Overview
Problem
The area of a semiconductor chip cannot be reduced effectively unless the area of the CMOS circuit is also minimized, as it is often determined by the size of the CMOS circuit, making it challenging to downsize the chip while maintaining efficient memory cell array operations.
Innovation Solution
The semiconductor device incorporates a CMOS circuit composed of transistors on two substrates, allowing for the reduction of the chip's area by distributing the transistors and memory cell array across multiple substrates, with one substrate having low-voltage transistors and the other high-voltage transistors, enabling flexible thickness adjustments to optimize chip size and functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the area of the memory cell array is reduced, then the area of the semiconductor chip can be reduced, but the area of the CMOS circuit also needs to be reduced to achieve effective chip downsizing
Solution Approach 1:
The patent divides the CMOS circuit into two separate substrates: a first substrate containing first transistors and a second substrate containing second transistors. This segmentation allows independent optimization of each substrate's area and complexity, enabling the memory cell array area to be reduced without being constrained by a monolithic CMOS circuit layout. The circuit functionality is distributed across substrates, achieving chip downsizing while managing complexity.
Solution Approach 2:
The patent transitions from a two-dimensional planar integration of CMOS circuits to a three-dimensional stacked architecture where multiple substrates are vertically arranged. The first and second substrates are positioned at different vertical levels, with the memory cell array spanning across them. This dimensional change allows the CMOS circuit area to be decoupled from the memory cell array area, enabling independent optimization and effective chip downsizing.
2Area of stationary object
If transistors are distributed across multiple substrates, then the chip area can be minimized, but the structural complexity of the device increases
Solution Approach 1:
The patent creates a universal substrate structure where both the first substrate and second substrate serve dual purposes: they individually host transistors for the CMOS circuit while collectively supporting the memory cell array structure. The substrates function as both circuit carriers and structural foundations for the vertical memory architecture, reducing the need for additional support structures and minimizing overall chip area despite the multi-substrate configuration.
Solution Approach 2:
The patent implements a nested arrangement where the memory cell array structure is vertically integrated across the first and second substrates. The substrates are positioned within the same vertical footprint, with the memory cell array spanning between them. This nesting allows the multi-substrate structure to occupy minimal planar area while maintaining the necessary structural complexity for distributed transistor implementation.
Data Source
AI summary
In one embodiment, a semiconductor device includes a first substrate, a first transistor provided on an upper face of the first substrate, and a memory cell array provided above the first transistor. The device further includes a second substrate provided above the memory cell array, and a second transistor provided on an upper face of the second substrate.