3D Stacked Memory CMOS Structure RC Delay Reduction
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Solution Overview
Problem
In semiconductor technology, there is a challenge to reduce the volume of semiconductor elements while enhancing chip performance, particularly in reducing the RC delay time of local bit lines and source lines within a fixed volume.
Innovation Solution
A semiconductor structure is designed with a CMOS structure, including a staircase decoder, positioned below a stack of memory cells, allowing for the alternately arranged and connected local bit lines and source lines, which reduces the size of the memory device and manufacturing costs, thereby enhancing chip performance by minimizing RC delay time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the CMOS structure is disposed below the stack of memory cells, then the size of the memory device is reduced, but the manufacturing complexity increases
Solution Approach 1:
The patent transitions from a planar layout to a three-dimensional stacked architecture by disposing the CMOS structure below the memory cell stack. This vertical integration utilizes the Z-dimension to reduce the footprint area while maintaining functional separation between the CMOS circuitry and memory cells, effectively resolving the size-reduction goal despite increased manufacturing complexity
2Loss of time
If local bit lines and local source lines are arranged alternately and connected to transistors, then the RC delay time is reduced, but the device structure becomes more complex
Solution Approach 1:
The bit lines and source lines are segmented into local segments that are alternately arranged and independently connected to bit line transistors and source line transistors. This segmentation reduces the length of each local bit line and source line, thereby reducing the RC delay time while distributing the structural complexity across multiple smaller components rather than one large interconnected structure
Data Source
AI summary
A semiconductor structure includes a stack of memory cells and a CMOS structure. The CMOS structure is located below the stack of memory cells. The CMOS structure includes a source line transistor and a bit line transistor.