Stacked Semiconductor Memory Device Columnar Arrangement
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Solution Overview
Problem
High integration in stacked type semiconductor memory devices leads to increased resistance in electrode films, affecting the operation speed and reliability of the devices.
Innovation Solution
The semiconductor memory device design includes a specific arrangement of columnar members with a lower arrangement density in the center portion, reducing void formation and electric resistance by providing an insulating support that facilitates a current path with less interposition, thereby improving operation speed and preventing device collapse.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high integration is implemented in stacked type semiconductor memory devices, then memory cell density is improved, but electrode film resistance increases
Solution Approach 1:
The patent applies local quality by creating different columnar member arrangements in different regions: the center portion has a lower arrangement density (every other columnar member present) compared to the side portions (continuous arrangement). This local differentiation reduces void formation and improves current flow in the center region where high integration would otherwise cause excessive resistance, thereby resolving the contradiction between high memory cell density and acceptable electrode film resistance.
2Stability of the object's composition
If columnar members are densely arranged to support the stacked body, then structural stability is improved, but void formation increases and electric resistance increases
Solution Approach 1:
The patent implements local quality by varying the columnar member arrangement density across different regions. The side portions maintain high density for structural support, while the center portion uses lower density (alternating pattern) to reduce void formation and improve current flow, thus resolving the contradiction between structural stability and electrical performance.
Solution Approach 2:
The patent resolves the contradiction by transitioning from a uniform two-dimensional arrangement to a three-dimensional patterned arrangement in the center portion, where columnar members are selectively positioned in an alternating pattern. This dimensional approach allows simultaneous optimization of structural support and electrical conductivity.
Data Source
AI summary
A semiconductor memory device includes a first electrode layer extending in a first direction, a second electrode layer above the first electrode layer and extending in the first direction, a third electrode layer above the first electrode layer and extending in the first direction, an insulating member between the second and third electrode layers and extending in the first direction, first semiconductor members extending in the second direction through the first and second electrodes, second semiconductor members extending in the second direction through the first and third electrode layers, and third semiconductor members extending in the second direction, each having a first portion between the second and third electrode layers and in contact with the insulating member, and a second portion extending through the first electrode layer. In the first direction, an arrangement density of the third semiconductor members is lower than that of the first or second semiconductor member.