Stacked Memory Cell Bonding with a Common Source Layer
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Solution Overview
Problem
The downscaling of semiconductor pads and wires makes it increasingly difficult to precisely align them during bonding, leading to challenges in achieving adequate electrical connections.
Innovation Solution
A semiconductor storage device configuration where source layers SL1 and SL2 are directly joined and function as an integrated common source layer, allowing for easier alignment and ensuring electrical connection even with slight misalignment, and a manufacturing method involving the formation of interlayer dielectric films and multilayered wire layers to connect memory cell arrays and control circuit layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If pads or wires are downscaled to increase integration density, then device capacity increases, but alignment precision during bonding deteriorates
Solution Approach 1:
The bonding interface is segmented into two distinct types: pads (for electrical connection) and alignment marks (for positional alignment). This segmentation allows the alignment mark to be larger and easier to align than the actual electrical pads, resolving the contradiction between small pad size and alignment precision.
Solution Approach 2:
An alignment mark structure is introduced as an intermediary element between the bonding surfaces. This marker serves as a mediator that facilitates precise alignment without requiring the actual electrical pads to be large, thus enabling both high integration density and accurate alignment.
2Quantity of substance
If pads are made smaller to increase device capacity, then integration density improves, but electrical connection reliability deteriorates
Solution Approach 1:
The bonding interface is segmented into two distinct types: pads (for electrical connection) and alignment marks (for positional alignment). This segmentation allows the alignment mark to be larger and easier to align than the actual electrical pads, resolving the contradiction between small pad size and alignment precision.
Solution Approach 2:
An alignment mark structure is introduced as an intermediary element between the bonding surfaces. This marker serves as a mediator that facilitates precise alignment without requiring the actual electrical pads to be large, thus enabling both high integration density and accurate alignment.
Data Source
AI summary
A semiconductor storage device includes a first layer including a first surface and a second surface located opposite to the first surface. The first layer includes a first memory cell array and a first wire layer, the first memory cell array being provided between the first surface and the second surface and including a plurality of first memory cells, and the first wire layer facing the first surface and being electrically connected to the first memory cells. A second layer includes a third surface and a fourth surface located opposite to the third surface. The second layer includes a second memory cell array provided between the third surface and the fourth surface to be electrically connected to the first wire layer and including a plurality of second memory cells. The first layer and the second layer are joined together on the first surface and the third surface.