3D Stacked Memory Computing Device Bandwidth Optimization
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Solution Overview
Problem
Large-scale computing systems face limitations in securing sufficient bandwidth for information exchanges between processors and memories, particularly due to constraints in input/output (I/O) bandwidth, which hampers computational performance.
Innovation Solution
The implementation of a computing device with a processor, a memory stack, and a substrate where the network bandwidth between the processor and the substrate is five or less times the memory bandwidth, allowing for independent adjustment of memory and network bandwidth through TSV connections and I/O connections, respectively, to optimize computational performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of applied problem processed in large-scale computing system is increased, then computational performance is improved, but information exchange bandwidth between processors and memories becomes insufficient
Solution Approach 1:
The patent transitions from traditional 2D processor-memory architecture to a 3D stacked architecture where memories are vertically stacked above processors. This dimensional change enables significantly increased bandwidth by providing multiple parallel data paths through vertical interconnects (TSVs), directly addressing the bandwidth insufficiency when processing large-scale problems.
Solution Approach 2:
The computing system is segmented into independent processing units, each with its own locally-attached memory stack. This segmentation allows parallel information exchange across multiple processor-memory pairs, collectively providing sufficient aggregate bandwidth for large-scale computational tasks while maintaining high bandwidth-per-processor ratios.
2Device complexity
If network bandwidth is increased relative to memory bandwidth, then system integration is improved, but computational performance becomes limited by I/O bandwidth
Solution Approach 1:
The patent changes the bandwidth ratio parameter between network I/O and memory access by implementing high-bandwidth memory stacks with sufficient TSV connections. This ensures memory bandwidth scales proportionally with network bandwidth, preventing I/O bottlenecks while maintaining balanced system integration across different computational workloads.
Data Source
AI summary
A computing device includes: a processor; a memory stack in which memories connected to the processor are stacked; and a substrate disposed under the processor, wherein a network bandwidth between the processor and the substrate is five or less times a memory bandwidth between the processor and the memory stack.