Stacked Memory Device Independent Connection Layer
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Solution Overview
Problem
Current nonvolatile resistive memory devices with stacked 3D configurations face challenges in efficiently connecting memory cell selecting lines to functional circuits, limiting flexibility and scalability in memory cell array layer configurations.
Innovation Solution
The implementation of a stacked semiconductor memory device with a connection layer above the semiconductor substrate, independent of memory cell array layers, which electrically connects memory cell selecting lines, such as bitlines and wordlines, to a functional circuit, allowing for flexible configuration and scalability by using horizontal and vertical connection lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell array layers are stacked in a 3-dimensional configuration to improve storage density, then storage capacity increases, but the complexity of connecting memory cell selecting lines to functional circuits increases
Solution Approach 1:
The patent transitions from planar 2D connections to 3D vertical connections by stacking memory cell array layers above the semiconductor substrate. Connection lines extend vertically through the stacked structure, enabling multi-layer access and increasing storage density while managing connection complexity through systematic routing patterns.
Solution Approach 2:
The patent divides the memory device into distinct functional segments: a semiconductor substrate containing functional circuits, and multiple stacked memory cell array layers. This segmentation allows independent optimization of each layer and simplifies the connection architecture by creating modular units that can be systematically interconnected through connection lines.
2Quantity of substance
If memory cell array layers are stacked to increase storage capacity, then data retention capability improves, but the flexibility of configuring memory cell selecting lines deteriorates
Solution Approach 1:
The connection lines are designed with universal routing capabilities that can connect to functional circuits on the substrate and to corresponding selecting lines on multiple stacked memory cell array layers. This multi-functional connection structure maintains configuration flexibility while supporting increased storage capacity through vertical stacking.
3Quantity of substance
If memory cell array layers are stacked above the semiconductor substrate, then integration density improves, but the difficulty of manufacturing and assembling the device increases
Solution Approach 1:
The patent forms connection lines that extend from the substrate surface upward in advance, before the memory cell array layers are fully assembled. This preliminary action simplifies subsequent manufacturing steps by pre-establishing the vertical connection pathways needed for integrating stacked memory layers, reducing assembly complexity while maintaining high integration density.
Data Source
AI summary
A stacked semiconductor memory device comprises a semiconductor substrate having a functional circuit, a plurality of memory cell array layers, and at least one connection layer. The memory cell array layers are stacked above the semiconductor substrate. The connection layers are stacked above the semiconductor substrate independent of the memory cell array layers. The connection layers electrically connect memory cell selecting lines arranged on the memory cell array layers to the functional circuit.