3D Memory Gate and Source Contact Structure for Noise Reduction
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high data storage capacity and reliable electrical characteristics, particularly in three-dimensionally arranged memory cells, where noise from the common source line affects read operations due to high electrical resistance.
Innovation Solution
The semiconductor device incorporates a second substrate with insulating patterns and gate electrodes, channel structures, and contact plugs to reduce noise by providing a low-resistance electrical connection path from the source contact plug to the channel structure, improving electrical characteristics and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensionally arranged memory cells are used to increase data storage capacity, then storage capacity is improved, but electrical resistance increases causing noise in read operations
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional arrangement by stacking multiple substrates vertically. This dimensional change increases storage capacity while the patent addresses the resulting electrical resistance issue by introducing dedicated contact plugs and low-resistance connection paths in the vertical dimension to maintain signal integrity.
Solution Approach 2:
The patent divides the three-dimensional memory structure into multiple substrates stacked vertically, with each substrate containing memory cells. This segmentation allows for better management of electrical connections by providing separate contact plugs for each substrate level, reducing the cumulative electrical resistance and noise in read operations.
2Quantity of substance
If three-dimensionally arranged memory cells are used to increase data storage capacity, then storage capacity is improved, but noise from common source line affects read operations
Solution Approach 1:
The patent extracts the source line connection function from the common source line structure and implements dedicated source contact plugs for each substrate level. This separation removes the noise coupling effect that occurs in shared common source lines, allowing each memory cell string to have its own low-impedance source connection and eliminating the harmful noise interference in read operations.
3Reliability
If gate contact plugs extend into insulating patterns, then electrical connection is improved, but manufacturing complexity increases
Solution Approach 1:
The patent forms insulating patterns in the substrate before forming the gate contact plugs. This preliminary action creates predefined low-resistance paths through the substrate, guiding the contact plug formation process and simplifying the overall manufacturing by establishing the electrical connection route in advance rather than creating complex three-dimensional connections simultaneously.
Data Source
AI summary
A semiconductor device includes a substrate including a first region and a second region; insulating patterns in the substrate; gate electrodes provided below the substrate and spaced apart from each other in a first direction that is perpendicular to a lower surface of the substrate, the gate electrodes including pad regions arranged in a step shape below the second region; gate contact plugs passing through the pad regions of the gate electrodes, extending in the first direction, and vertically overlapping the insulating patterns; and a peripheral contact plug provided in an outer area of the substrate and extending from a level lower than a level of a lowermost gate electrode of the gate electrodes to a level higher than the lower surface of the substrate; and conductive patterns including a first conductive pattern provided on and connected to the peripheral contact plug, and second conductive patterns provided on and connected to the substrate.