3D Memory Gate Contact Sequencing for Reliable Vertical Connections
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor memory devices face challenges in increasing data storage capacity while maintaining performance and reliability, particularly in three-dimensional memory cell arrangements.
Innovation Solution
A semiconductor memory device with a stacked structure of mold insulating films and gate electrodes, featuring gate contacts that are sequentially connected to gate electrodes, and a channel structure penetrating the stacked structure, allowing for improved electrical connectivity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged three-dimensionally to increase data storage capacity, then storage capacity is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional stacked structure, where multiple memory cell layers are vertically stacked above each other. This dimensional change enables significantly increased storage capacity within the same footprint area, directly resolving the contradiction between storage capacity and device footprint.
Solution Approach 2:
The memory device is divided into multiple discrete memory cell layers stacked vertically, with each layer containing complete sets of word lines, bit lines, and memory cells. This segmentation into modular layers allows for systematic manufacturing and electrical connection management, reducing the complexity burden of the three-dimensional structure.
2Reliability
If gate contacts are extended through the stacked structure to connect multiple gate electrodes, then electrical connectivity is improved, but contact hole formation complexity and manufacturing precision requirements increase
Solution Approach 1:
The patent implements varying gate contact lengths tailored to specific electrical connection needs. Gate contacts are extended to different depths to connect to different numbers of gate electrodes (first gate contact connects to first through third gate electrodes, second gate contact connects to second through fourth gate electrodes, etc.). This local differentiation optimizes electrical connectivity for each contact while managing manufacturing complexity through standardized patterns.
3Reliability
If gate contacts are made longer to penetrate deeper into the stacked structure, then electrical connection reliability is improved, but stress on the gate electrodes and structural integrity may deteriorate
Solution Approach 1:
Different gate contacts are designed with different lengths based on their specific electrical connection requirements. The first gate contact extends to connect to gate electrodes closer to the substrate, while the second gate contact extends further to connect to gate electrodes farther from the substrate. This localized optimization ensures adequate electrical connection reliability without uniformly increasing stress across all contacts.
Solution Approach 2:
The patent incorporates stress management considerations in the gate contact design from the outset. By carefully controlling gate contact lengths and their penetration depths into the stacked structure, the design preemptively mitigates potential stress concentration issues that could compromise structural integrity, while still achieving reliable electrical connections.
Data Source
AI summary
A semiconductor memory device includes a substrate; a stacked structure which includes a plurality of mold insulating films and a plurality of gate electrodes that are alternately stacked on the substrate; and a plurality of gate contacts that penetrate at least a part of the stacked structure, and are electrically connected to the plurality of gate electrodes, wherein the plurality of gate contacts include first to n-th gate contacts (n is a natural number of 3 or more) arranged in sequence along a first direction, the first to (j−1)-th gate contacts are respectively electrically connected to gate electrodes closer to the substrate as they are closer to a j-th gate contact (j is a natural number equal to or greater than 2 and less than n), and the (j+1)-th to n-th gate contacts are respectively electrically connected to gate electrodes that are further from the substrate, as they are further away from the j-th gate contact.