3D Memory Contact Structure With Integral Low-Resistance Connections
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices face challenges in achieving high data storage capacity and efficient operation, particularly in terms of operating speed and reliability, especially in three-dimensional memory cell configurations.
Innovation Solution
A semiconductor device design featuring a first semiconductor structure with circuit elements and lower interconnection lines, and a second semiconductor structure with gate electrodes, interlayer insulating layers, through-insulating regions, and conductive patterns that include integral connection portions to enhance electrical connectivity and reduce resistance, thereby improving operating speed and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional memory cell configurations are used to increase data storage capacity, then storage capacity is improved, but operating speed and reliability deteriorate due to increased resistance and connectivity issues
Solution Approach 1:
The patent merges the first contact plug and connection portion into an integral conductive pattern, eliminating the interface between separate components. This reduces contact resistance and improves reliability in three-dimensional memory structures by creating a continuous conductive path from the gate electrode to the lower interconnection lines.
Solution Approach 2:
The patent transitions from two-dimensional planar connections to three-dimensional vertical stacking with conductive patterns that extend through multiple layers. The connection portion extends to surround the first contact plug in a three-dimensional configuration, enabling efficient electrical connectivity in vertically stacked memory cells.
2Quantity of substance
If three-dimensional memory cell configurations are used to increase data storage capacity, then storage capacity is improved, but operating speed deteriorates due to increased resistance
Solution Approach 1:
The integration of the first contact plug and connection portion into a single conductive pattern eliminates interfacial contact resistance, creating a continuous low-resistance path for electrical signals. This improves operating speed in three-dimensional memory devices by reducing the total resistance in the signal path.
3Ease of manufacture
If separate contact plugs and connection portions are used in stacked structures, then manufacturing flexibility is improved, but electrical connectivity and resistance performance deteriorate
Solution Approach 1:
The patent combines the previously separate first contact plug and connection portion into a single integral conductive pattern formed by depositing conductive material and patterning it in one process step. This eliminates the interface between components, reducing contact resistance and improving electrical connectivity while maintaining ease of manufacture through standard semiconductor fabrication processes.
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
A semiconductor device includes a first semiconductor structure including a first substrate and a second semiconductor structure on the first semiconductor structure. The second semiconductor structure includes gate electrodes stacked on the second substrate, interlayer insulating layers alternately stacked with the gate electrodes, through-insulating regions passing through the gate electrodes in a second region, a capping insulating layer covering the gate electrodes and the interlayer insulating layers, an upper insulating layer on the capping insulating layer, channel structures passing through the capping insulating layer and the gate electrodes in a first region, upper contact plugs passing through the upper insulating layer, bit lines on the upper insulating layer, first contact plugs passing through the capping insulating layer, and conductive patterns including second contact plugs passing through each of the through-insulating regions in the second region. The conductive patterns include connection portions integral with the second contact plugs.