Stacked Memory Control Logic Layout for Higher Density NAND
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Solution Overview
Problem
Conventional microelectronic device designs face challenges in increasing memory density and performance due to processing conditions and the complexity of control logic devices, which often consume more space and hinder reductions in size and operational efficiency.
Innovation Solution
The solution involves forming a microelectronic device with a first microelectronic device structure containing a memory array region and associated circuitry, and a second microelectronic device structure comprising control logic devices, where the two structures are fabricated separately under different processing conditions, allowing for the inclusion of high-performance, low-voltage transistors and logic devices optimized for specific operations, such as page buffers, which reduces the horizontal footprint and enhances memory density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If control logic devices are formed within a base control logic structure underlying the memory array, then control operations can be performed, but the processing conditions limit the configurations and performance of the control logic devices
Solution Approach 1:
The device is divided into two separate structures: a first microelectronic device structure containing the memory array region, and a second microelectronic device structure containing the control logic devices. This segmentation allows each structure to be fabricated under optimized processing conditions independent of the other, resolving the contradiction between manufacturing constraints and device performance.
Solution Approach 2:
The control logic devices are extracted from the base control logic structure and placed in a separate second microelectronic device structure. This extraction enables the control logic devices to be formed under different, more favorable processing conditions while maintaining their functional connection to the memory array through the interconnect region.
2Ease of operation
If control logic devices are included in the base control logic structure, then memory operations can be controlled, but the quantities, dimensions, and arrangements impede reductions to the size of the memory device
Solution Approach 1:
The control logic devices are moved from a planar arrangement in the base control logic structure to a vertical stacking configuration in a separate second microelectronic device structure. This dimensional change allows the control logic to be positioned above or below the memory array, reducing the horizontal footprint while maintaining operational control.
Solution Approach 2:
By separating the control logic devices into a distinct second microelectronic device structure, the design allows for independent optimization of the memory array region and control logic region, enabling more efficient space utilization and reduced overall device footprint.
3Ease of operation
If control logic devices are formed within the base control logic structure, then memory operations can be controlled, but the control logic devices consume more real estate, reducing the memory density
Solution Approach 1:
The control logic devices are relocated to a separate vertical structure, allowing the memory array region to occupy maximum horizontal space for high density, while the control logic resides in the vertical dimension, thus increasing overall memory density without sacrificing operational control capability.
4Quantity of substance
If conventional vertical memory array architectures are used, then memory density can be increased, but the control logic complexity increases with the memory array density
Solution Approach 1:
By separating the control logic devices into a distinct second microelectronic device structure, the design decouples the complexity of high-density memory arrays from the control logic, allowing independent optimization of both regions and managing complexity more effectively.
Data Source
AI summary
A microelectronic device comprises a first die comprising a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, and vertically extending strings of memory cells within the stack structure. The first die further comprises a first control logic region comprising a first control logic device including at least a word line driver. The microelectronic device further comprises a second die attached to the first die, the second die comprising a second control logic region comprising second control logic devices including at least one page buffer device configured to effectuate a portion of control operations of the vertically extending string of memory cells. Related microelectronic devices, electronic systems, and methods are also described.