Stacked Memory Array and Control Logic for Higher DRAM Density
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Solution Overview
Problem
Microelectronic device designers face challenges in reducing the size and improving the performance of memory devices, such as DRAM, due to processing conditions and the configuration of control logic devices, which limit feature integration density and performance enhancements.
Innovation Solution
The method involves forming microelectronic devices with vertically offset control logic devices within array regions, using specific configurations of array, digit line exit, word line exit, and socket regions, and employing conductive and insulative materials to optimize the arrangement and performance of memory cells and control logic circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If control logic devices are formed using conventional processing conditions, then the memory array can be fabricated, but the control logic device configurations and performance are limited
Solution Approach 1:
The device is segmented into two separate structures: a first microelectronic device structure containing the memory array, and a second microelectronic device structure containing the control logic devices. These structures are formed separately under different processing conditions and then attached together, allowing each to be optimized independently for its specific function without compromise.
Solution Approach 2:
The control logic devices are extracted from the conventional integrated memory array structure and placed in a separate second microelectronic device structure. This extraction allows the control logic devices to be formed under optimized processing conditions independent of the memory array fabrication constraints.
2Productivity
If conventional control logic device arrangements are used, then the memory device can function, but the horizontal footprint size is increased
Solution Approach 1:
The invention transitions from a two-dimensional planar arrangement to a three-dimensional stacked architecture. Control logic devices are positioned in a third dimension (vertical direction) relative to the memory array, enabling higher integration density without increasing the horizontal footprint area.
Solution Approach 2:
The second microelectronic device structure containing control logic devices is positioned to overlap horizontally with the first microelectronic device structure containing the memory array. This nesting arrangement allows both structures to share the same horizontal footprint, effectively doubling the functional density within the same area.
3Reliability
If conventional processing conditions are used for the memory array, then fabrication is straightforward, but control logic device performance and switching characteristics are degraded
Solution Approach 1:
The fabrication process is segmented into two independent manufacturing flows: one for the memory array under conventional processing conditions, and another for the control logic devices under optimized processing conditions. This segmentation allows each structure to be manufactured using the most appropriate process conditions for its specific requirements, improving overall device performance despite increased process complexity.
Solution Approach 2:
Both the first and second microelectronic device structures are completely formed and optimized separately before being attached together. This preliminary action allows full optimization of control logic device performance characteristics before integration, ensuring that performance is not compromised by subsequent processing steps.
4Productivity
If control logic devices are integrated with the memory array, then electrical communication is established, but the quantities and dimensions of control logic devices impede performance improvements
Solution Approach 1:
The control logic devices are positioned in a vertical dimension above the memory array rather than being laterally integrated. This dimensional change reduces the number of control logic devices needed within the horizontal plane and simplifies their arrangement, while still enabling efficient electrical communication through vertical interconnects.
Solution Approach 2:
The first and second microelectronic device structures are attached together to form a single integrated assembly. This merging combines the memory array and control logic devices into one functional unit with optimized electrical connections, improving data transfer rates while reducing the overall complexity of separate interconnected components.
Data Source
AI summary
A method of forming a microelectronic device comprises forming a microelectronic device structure assembly comprising memory cells, digit lines coupled to the memory cells, contact structures coupled to the digit lines, word lines coupled to the memory cells, additional contact structures coupled to the word lines, and isolation material surrounding the contact structures and the additional contact structures and overlying the memory cells. An additional microelectronic device structure assembly is formed and comprises control logic devices, further contact structures coupled to the control logic devices, and additional isolation material surrounding the further contact structures and overlying the control logic devices. The additional microelectronic device structure assembly is attached to the microelectronic device structure assembly by bonding the additional isolation material to the isolation material and by bonding the further contact structures to the contact structures and the additional contact structures. Microelectronic devices and electronic systems are also described.