Stacked Memory Array Layout With Separated Control Circuits
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Solution Overview
Problem
Increasing storage density in semiconductor devices is challenging due to physical limitations, electrical interference, and manufacturing difficulties, which affect the efficiency and cost of data storage in consumer electronics, data centers, and mobile devices.
Innovation Solution
The semiconductor device features a control semiconductor structure and array semiconductor structures stacked along a vertical direction, with peripheral circuits integrated into the control semiconductor structure, allowing for larger pitches in via connections and simplified manufacturing processes, and enabling separate fabrication to manage thermal budgets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If array semiconductor structures are stacked vertically to increase storage density, then storage capacity increases, but manufacturing complexity and thermal management difficulty increase
Solution Approach 1:
The semiconductor device is divided into multiple independent array semiconductor structures stacked vertically, each with its own control circuits. This segmentation allows each stack to be manufactured and tested separately before final assembly, reducing overall manufacturing complexity while achieving high storage density through vertical stacking.
Solution Approach 2:
The patent transitions from traditional planar 2D memory architecture to a 3D vertical stacking architecture. Multiple array semiconductor structures are stacked along the vertical direction, utilizing the third dimension to increase storage capacity without proportionally increasing footprint area or manufacturing complexity.
2Area of stationary object
If control circuits are integrated into the same chip as array structures, then chip area is reduced, but manufacturing yield and thermal management become more difficult
Solution Approach 1:
Control circuits for each array semiconductor structure are integrated into the same stack rather than being separate on the chip. This segmentation approach allows each stacked unit to be independently manufactured and tested, improving yield by isolating defects to individual stacks while still achieving compact chip area through vertical integration.
Solution Approach 2:
Control circuits are nested within the array semiconductor structure stacks, with control circuits positioned at the bottom of each stack. This nested configuration reduces chip area by eliminating separate control circuit regions while maintaining manufacturing yield through modular stack construction and independent testing.
3Quantity of substance
If via connection pitches are reduced to increase interconnect density, then storage density increases, but manufacturing precision requirements and cost increase
Solution Approach 1:
Instead of increasing interconnect density by reducing via pitches in the planar direction, the patent utilizes vertical stacking to achieve higher storage density. The via connections between stacked arrays maintain standard pitch dimensions, avoiding the need for ultra-precise via alignment while still achieving high interconnect density through the third dimension.
Data Source
AI summary
The present disclosure relates to methods, devices, systems, and techniques for managing semiconductor devices with stacked structures. An example semiconductor device includes a control semiconductor structure and array semiconductor structures. The array semiconductor structures are stacked along a first direction and are coupled to the control semiconductor structure. The array semiconductor structures include at least a first array semiconductor structure and a second array semiconductor structure. The first array semiconductor structure includes: a first array region; a first connection region adjacent to the first array region along a second direction perpendicular to the first direction; first bit line connection structures in the first array region; first word line contact structures extending along the first direction in the first connection region; and first word line connection structures extending along the first direction in the first connection region.