Stacked Memory With Off-Chip Controller Segmentation
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Solution Overview
Problem
The high cost of manufacturing high-density memory devices is exacerbated by the need for different manufacturing steps for memory technologies and supporting peripheral circuits, leading to increased expenses and potential compromises in circuitry.
Innovation Solution
The implementation of a stacked structure with complementary interconnect surfaces for memory and peripheral circuits, allowing for separate fabrication processes and independent technologies, enabling cost-effective manufacturing by separating the memory and peripheral circuitry into different layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If memory circuit and peripheral circuit are manufactured together on the same chip, then integration is improved, but manufacturing cost increases due to requiring different manufacturing steps for memory technologies and supporting peripheral circuits
Solution Approach 1:
The patent divides the memory device into separate modules: a memory circuit layer and a peripheral circuit layer. These layers are manufactured independently using different fabrication processes optimized for each circuit type, then stacked and interconnected. This segmentation allows each layer to be manufactured using the most appropriate process technology without compromise, reducing overall manufacturing cost while maintaining integration.
Solution Approach 2:
The patent transitions from planar integration to three-dimensional stacking, placing the memory circuit and peripheral circuit on separate layers stacked vertically. This dimensional change enables independent manufacturing of each layer using different processes, while achieving high integration through vertical interconnection via through-silicon vias (TSVs) and interconnect structures.
2Adaptability or versatility
If different manufacturing processes are used for memory array and peripheral circuit, then manufacturing flexibility is improved, but device complexity increases
Solution Approach 1:
By segmenting the device into separately manufacturable layers, the patent enables different fabrication processes to be applied to each layer independently. The memory circuit layer can use processes optimized for high-density storage, while the peripheral circuit layer can use processes optimized for logic and control functions, thereby increasing manufacturing flexibility without significantly increasing overall device complexity.
Solution Approach 2:
The patent introduces intermediary structures including interconnect layers, through-silicon vias (TSVs), and bonding interfaces that mediate between the separately manufactured memory and peripheral circuit layers. These intermediaries provide standardized interfaces and connection mechanisms that simplify the integration process, reducing the complexity burden that would otherwise result from using different manufacturing processes.
Data Source
AI summary
An integrated circuit memory device, including a memory circuit and a peripheral circuit, is described which is suitable for low cost manufacturing. The memory circuit and peripheral circuit for the device are implemented in different layers of a stacked structure. The memory circuit layer and the peripheral circuit layer include complementary interconnect surfaces, which upon mating together establish the electrical interconnection between the memory circuit and the peripheral circuit. The memory circuit layer and the peripheral circuit layer can be formed separately using different processes on different substrates in different fabrication lines. This enables the use of independent fabrication process technologies, one arranged for the memory array, and another arranged for the supporting peripheral circuit. The separate circuitry can then be stacked and bonded together.