3D Stacked Memory Copper Pillar Interconnects
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Solution Overview
Problem
The high cost and complexity of through silicon via (TSV) technologies in 3D stacked memory devices limit their widespread adoption due to expensive manufacturing processes and increased costs, while existing copper pillar interconnections face challenges in achieving high I/O density and low production costs.
Innovation Solution
The implementation of copper pillars electrically connecting package units in 3D stacked memory devices, allowing for high I/O density, low fabrication costs, and small area packaging by embedding copper traces or pads into dielectric layers and using bond on lead (BOL) interconnections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through silicon via (TSV) technology is used to interconnect chips in 3D stacked memory devices, then electrical performance and interconnect length are improved, but manufacturing cost and device complexity increase significantly
Solution Approach 1:
The patent extracts the copper interconnect structure from the silicon substrate and places it on an organic carrier board. This separation allows the copper pillars to be formed and connected without requiring complex TSV processing through the silicon wafer, thereby reducing manufacturing complexity while maintaining electrical performance
Solution Approach 2:
The patent introduces an organic carrier board as an intermediary substrate to hold the copper pillars and facilitate chip interconnection. This mediator enables simplified copper pillar formation and connection processes compared to direct TSV implementation in silicon, reducing device complexity while preserving electrical connectivity
2Reliability
If through silicon via (TSV) technology is used for chip interconnection, then electrical performance is improved, but production cost increases
Solution Approach 1:
The patent uses an organic carrier board as a temporary, cost-effective substrate for forming copper pillars and connecting chips. This disposable-like approach avoids the expensive silicon TSV processing while achieving the necessary electrical connections, thereby reducing production cost
Solution Approach 2:
The organic carrier board serves as a low-cost intermediary that enables simplified copper pillar interconnection without requiring expensive TSV fabrication processes, thus improving ease of manufacture while maintaining electrical performance
3Productivity
If copper pillar interconnections with solder bumps are used, then I/O density and package size are improved, but manufacturing process complexity increases
Solution Approach 1:
The patent merges the copper pillar formation and solder bump attachment processes into a single integrated structure on the organic carrier board. This combination simplifies the overall manufacturing process compared to separate complex package technologies, while achieving high I/O density and compact packaging
Data Source
AI summary
3D Stacked memory devices with copper pillars electrically connecting the package units are disclosed. A stacked package-on-package memory device includes a base chip package unit having a logic processing chip disposed on a base substrate; and a memory chip stack overlying the base chip unit. The memory chip stack includes a stack of packaged memory units. Each packaged memory unit including a memory chip on an IC substrate. Copper pillars are disposed on the back side of the IC substrate and electrically connected to the base substrate.